Merge remote-tracking branch 'origin/FLX-1691_felig_unconstrained_endpoints' into release-4.10

simulation/FELIX_Top/felig_sim_top_bnl712.vhd

@@ -77,6 +77,8 @@ architecture Behavioral of felig_sim_top_bnl712 is
 
   signal gt_txusrclk_i           : std_logic_vector(GBT_NUM-1 downto 0);
   signal gt_rxusrclk_i           : std_logic_vector(GBT_NUM-1 downto 0);  
+  
+  signal gbt_downlink0  : std_logic_vector(119 downto 0);
 
 --  signal gbt_tx_data_120b_array_i: txrx120b_type(0 to GBT_NUM-1);
 --  signal gbt_rx_data_120b_array_i: txrx120b_type(0 to GBT_NUM-1);  
@@ -126,7 +128,7 @@ begin
   pcie0_register_map_40_control.FMEMU_RANDOM_CONTROL.SELECT_RANDOM <= "0";
   pcie0_register_map_40_control.FMEMU_RANDOM_CONTROL.SEED <= (others=>'0');
   pcie0_register_map_40_control.FMEMU_RANDOM_CONTROL.POLYNOMIAL <= (others=>'0');    
-  pcie0_register_map_40_control.CR_REVERSE_10B.FROMHOST <= "0";
+  pcie0_register_map_40_control.CR_REVERSE_10B.FROMHOST <= "1"; --MSB
   
 	
 --	lane_control.global.lane_reset				<= '0';
@@ -171,11 +173,17 @@ begin
     emu_control(i).userdata			<= X"ABCD";
   end generate gen_emu_control;
 	
+--  emu_control(0).output_width	<= "00";
+--  emu_control(1).output_width	<= "00"; --"11";
+--  emu_control(2).output_width	<= "01";
+--  emu_control(3).output_width	<= "01";
+--  emu_control(4).output_width	<= "10";
+
   emu_control(0).output_width	<= "00";
-  emu_control(1).output_width	<= "00"; --"11";
-  emu_control(2).output_width	<= "01";
-  emu_control(3).output_width	<= "01";
-  emu_control(4).output_width	<= "10";
+  emu_control(1).output_width	<= "01"; --"11";
+  emu_control(2).output_width	<= "10";
+  emu_control(3).output_width	<= "10";
+  emu_control(4).output_width	<= "11";
   
 --  gen_elink_control_egroup_0 : for i in  0 to  7 generate
 --    elink_control(i).output_width	<= "10";
@@ -270,10 +278,10 @@ begin
         gbt_rx_reset	<= '1';
       elsif(time_count = 4600) then
         gbt_rx_reset	<= '0';
-      elsif(time_count = 4800) then
-        emu_reset <= '1';
-      elsif(time_count = 5000) then
-        emu_reset <= '0';
+--      elsif(time_count = 4800) then
+--        emu_reset <= '1';
+--      elsif(time_count = 5000) then
+--        emu_reset <= '0';
       elsif(time_count = 5600) then
         gbt_tx_reset <= '1';
       elsif(time_count = 5800) then
@@ -282,10 +290,10 @@ begin
         lane_control(0).global.l1a_counter_reset	<= '1';
       elsif(time_count = 6575) then
         lane_control(0).global.l1a_counter_reset    <= '0';
-      elsif(time_count = 10400) then
-        elink_sync <= '1';
-      elsif(time_count = 15800) then
-        elink_sync <= '0';
+--      elsif(time_count = 10400) then
+--        elink_sync <= '1';
+--      elsif(time_count = 15800) then
+--        elink_sync <= '0';
       end if;
     end if;
   end process;
@@ -366,6 +374,7 @@ begin
       
       );
 
+  gbt_downlink0 <= TX_120b_i(0);
 	
 --	FELIG_lane_wrapper_comp : entity work.FELIG_lane_wrapper
   EmulatorWrapper_comp : entity work.EmulatorWrapper        

sources/feligHG710/data_generator/elink_printer_bit_feeder_v2.vhd

@@ -53,6 +53,7 @@ architecture Behavioral of elink_printer_bit_feeder_v2 is
 	signal reg_160_8b10b        : std_logic_vector(159 downto 0) := (others => '0');
 	signal reg_160_direc        : std_logic_vector(159 downto 0) := (others => '0');
 
+	signal word_in_d	        : std_logic_vector(9 downto 0)	:= (others => '0');
 	signal word_test	        : std_logic_vector(9 downto 0)	:= (others => '0');
 	signal word_test_h	        : std_logic_vector(9 downto 0)	:= (others => '0');
 	signal word_test_l	        : std_logic_vector(9 downto 0)	:= (others => '0');	
@@ -61,6 +62,7 @@ architecture Behavioral of elink_printer_bit_feeder_v2 is
 	signal wr_to_reg            : std_logic := '0';
 	signal wr_to_reg_2b         : std_logic := '0';
 	signal wr_to_reg_final      : std_logic := '0';
+	signal wr_to_reg_final_d    : std_logic := '0';
 	signal count                : integer range 0 to 15;
 	signal count_max            : integer range 0 to 15;
 	signal count_to_five        : std_logic_vector(2 downto 0) := (others => '0');	
@@ -135,26 +137,13 @@ begin
           '1' when shift_op = "001" and input_width = '1' else
           read_enable_buf when input_width = '0' else 
           '0';
-  word_test <= word_test_l when output_width = "010" and input_width = '1' else
-               word_test_l when output_width = "100" and input_width = '1' else
-               word_test_h;
-  
+ 
 --  2*5 =  10  1 word
 --  4*5 =  20  2 words
 --  8*5 =  40  4 words
 -- 16*5 =  80  8 words 
 -- 32*5 = 160 16 words
-  
-  word_test_proc : process (flag)
-  begin
-    if flag'event and flag ='1' then
-      word_test_h <= word_in;
-    end if;
-    if flag'event and flag ='0' then
-      word_test_l <= word_in;
-    end if;
-  end process word_test_proc;
-  
+
   count_max <=  0 when output_width = "000" else -- 2b
                 1 when output_width = "001" else -- 4b
                 3 when output_width = "010" else -- 8b
@@ -173,7 +162,14 @@ begin
   begin
     if clk'event and clk ='1' then
       flag_d <= flag;
-      if wr_to_reg_final = '1' then
+      word_in_d <= word_in;
+      wr_to_reg_final_d <= wr_to_reg_final;
+      if flag = '0' and flag_d = '1' and (output_width = "010" or output_width = "100") and input_width = '1' then
+        word_test <= word_in_d;
+      elsif flag = '1' and flag_d = '0' and (output_width = "000" or output_width = "001" or output_width = "011") and input_width = '1' then
+        word_test <= word_in_d;
+      end if;
+      if wr_to_reg_final_d = '1' then
         reg_160_8b10b((count+1)*10 - 1 downto count*10) <= word_test;
         reg_160_direc((count+1)*8  - 1 downto count*8 ) <= word_test(7 downto 0);
         if count = count_max then