FLX-2355 updated axi encoder TB

simulation/ItkStrip/tb_l0a_frame_generator.vhd

@@ -161,9 +161,13 @@ begin
             --                end if;
             --                wait until rising_edge(clk);
             --            end loop;
-
+            wait until rising_edge(ITk_sync_i);
             l0a_trig_i <= l0a_mask;
             l0id_i <= l0_tag;
+            wait until rising_edge(ITk_sync_i);
+            --wait until rising_edge(clk);
+            l0a_trig_i <="0000";
+            l0id_i <= (others => '0');
 
         end;
 
@@ -213,6 +217,8 @@ begin
                     l0_tag    => l0_tag_tmp,
                     l0a_mask  => l0a_mask_tmp
                 );
+                l0a_mask_expected <= "0000";
+                l0_tag_expected   <= (others => '0');
                 wait until rising_edge(clk);
 
             end loop;

simulation/ItkStrip/tb_lcb_axi_encoder.vhd

@@ -162,8 +162,8 @@ architecture RTL of tb_lcb_axi_encoder is
     constant command_channel : integer := 4;
 
     -- DUT internal signals
-    signal frame_phase_reg : std_logic_vector(15 downto 0); -- not used
-    signal bcr_delay_reg : std_logic_vector(15 downto 0); --not used
+    --signal frame_phase_reg : std_logic_vector(15 downto 0); -- not used
+    --signal bcr_delay_reg : std_logic_vector(15 downto 0); --not used
     signal dut_regmap :t_register_map;
     signal l0a_trig_i : std_logic_vector(3 downto 0); -- generated externally
     signal  sync_i : std_logic := '0'; --generated externally
@@ -212,7 +212,7 @@ begin
 
             -- TTC signals
             bcr_i                => bcr, --a clock cycle ahead of the nearest sync
-            l0a_i                => l0a,
+            l0a_i                => l0a, --not used
             l0a_trig_i           => l0a_trig_i,
             l0id_i               => l0id,
 
@@ -259,8 +259,8 @@ begin
     is_locked_o       <= frame.locked;
     --frame_start_pulse <= << signal DUT.frame_start_pulse : std_logic >>;
     --dut_regmap <= << signal DUT.LCB_inst.regmap : t_register_map >>;
-    frame_phase_reg <= dut_regmap(L0A_FRAME_PHASE); --not used
-    bcr_delay_reg <= dut_regmap(TTC_BCR_DELAY); --not used
+    --frame_phase_reg <= dut_regmap(L0A_FRAME_PHASE); --not used
+    --bcr_delay_reg <= dut_regmap(TTC_BCR_DELAY); --not used
 
     p_test : process is
         variable frame_rnd           : std_logic_vector(11 downto 0); -- L0 frame
@@ -290,7 +290,7 @@ begin
             variable bcr_time : integer range 0 to 3;
         begin
             log(ID_SEQUENCER_SUB, "Sending L0A frame: " & to_hstring(bcr_expected & mask & tag));
-            wait until rising_edge(frame_start_pulse);
+            wait until rising_edge(sync_i);
             -- determine when to assert BCR as to not affect the frame phase
             --            case frame_phase_reg(1 downto 0) is
             --                when "00"   => bcr_time := 1;
@@ -321,9 +321,12 @@ begin
 
             --bcr <= '0';
             --l0a <= '0';
-            l0id <= tag;
+            l0id <= tag when (not randomize_tag) else random(tag'length);
             l0a_trig_i <= mask; --"000";
             wait until rising_edge(clk);
+            l0id <= (others => '0');
+            l0a_trig_i <= "0000";
+
         end;
 
         -- simulates receiving a random L0A trigger (no BCR)
@@ -429,12 +432,12 @@ begin
         begin
             gen_pulse(decoder_rst, C_CYCLES_RST * C_CLK_PERIOD, "Reset frame decoder");
             wait until rising_edge(clk);
-            for i in 0 to 5 loop
-                bcr <= '1';
-                wait until rising_edge(clk);
-                bcr <= '0';
-                wait_num_rising_edge(clk, 31);
-            end loop;
+            --            for i in 0 to 5 loop
+            --                bcr <= '1';
+            --                wait until rising_edge(clk);
+            --                bcr <= '0';
+            --                wait_num_rising_edge(clk, 31);
+            --            end loop;
             check_value(is_locked_o, '1', ERROR, "Verifying that frame decoder is locked");
             check_value(phase_wrt_bcr_o, expected, ERROR, "Verifying frame phase with respect to BCR signal");
         end;
@@ -749,6 +752,7 @@ begin
         ) is
         begin
             log(ID_SEQUENCER, "Issuing BCR to start gating pulse generation");
+            wait until rising_edge(bcr);
             send_L0A( "0000", "0000000"); --'1',
             set_stopwatch;
             dequeue_next_frame;
@@ -780,6 +784,7 @@ begin
             variable interruption_roll :integer;
         begin
             log(ID_SEQUENCER, "Issuing BCR to start gating pulse generation");
+            wait until rising_edge(bcr);
             send_L0A("0000", "0000000"); --'1',
             dequeue_next_frame;
             check_value(next_frame.decoded, "100000000000", ERROR, "BCR frame received");
@@ -790,6 +795,8 @@ begin
                 interruption_roll := random(1,10);
                 if interruption_roll = 1 then
                     -- interrupt with L0A frame
+                    wait until rising_edge(bcr);
+                    wait_num_rising_edge(clk, 3);
                     send_L0A( mask => "1011", tag => "0100111"); --bcr_i => '0',
                 elsif interruption_roll = 2 then
                     -- interrupt with bypass frame
@@ -829,7 +836,8 @@ begin
         frame_queue.set_scope(C_TB_SCOPE_DEFAULT);
         start_clock(CLOCK_GENERATOR_VVCT, 1, "Start clock generator (BC clock)");--@suppress
         start_clock(CLOCK_GENERATOR_VVCT, 5, "Start clock generator (AXI clock)");--@suppress
-        disable_log_msg(ALL_MESSAGES);
+        --temp
+        --disable_log_msg(ALL_MESSAGES);
         enable_log_msg(ID_LOG_HDR);
         enable_log_msg(ID_SEQUENCER);
         enable_log_msg(ID_SEQUENCER_SUB);
@@ -854,7 +862,7 @@ begin
         gen_pulse(decoder_rst, C_CYCLES_RST * C_CLK_PERIOD, "Reset frame decoder");
         gen_pulse(rst, C_CYCLES_RST * C_CLK_PERIOD, "Reset DUT");
         wait for 1000 ns;
-        check_value(is_locked_o, '1', ERROR, "Frame decoder is locked after 500 ns");
+        check_value(is_locked_o, '1', ERROR, "Frame decoder is locked after 1000 ns");
         check_value(frame_queue.is_empty(void), false, ERROR, "Decoder received some frames");
         frame_var    := frame_queue.fetch(void);
         check_value(frame_var.idle, '1', ERROR, "Decoder received some IDLE frames");
@@ -912,12 +920,14 @@ begin
         log(ID_LOG_HDR, "Verifying that overall L0A frame delay can be adjusted");
         set_register(t_register_name'pos(TTC_L0A_ENABLE), x"0001");
         wait_num_rising_edge(clk, 50);
-        check_value(frame_phase_reg(1 downto 0), "00", "FRAME_PHASE is set to 00 for this test");--@suppress
-        check_value(bcr_delay_reg(11 downto 0), x"000", "L0A_BCR_DELAY is set to x000 for this test");--@suppress
+        --check_value(frame_phase_reg(1 downto 0), "00", "FRAME_PHASE is set to 00 for this test");--@suppress --not used
+        --check_value(bcr_delay_reg(11 downto 0), x"000", "L0A_BCR_DELAY is set to x000 for this test");--@suppress --not used
         for i in 0 to max_l0a_delay loop
             set_register(t_register_name'pos(L0A_FRAME_DELAY), std_logic_vector(to_unsigned(i, 16)));
             gen_pulse(decoder_rst, C_CYCLES_RST * C_CLK_PERIOD, "Reset frame decoder");
             await_value(is_locked_o, '1', 0 ns, 1 us,  ERROR, "Frame decoder is locked");
+            --wait until rising_edge(bcr);
+            --wait_num_rising_edge(clk, 3); -- BCR happened a while ago
             send_L0A( mask => "1111", tag => std_logic_vector(to_unsigned(i, 7)), randomize_tag => false); --bcr_i => '0',
             set_stopwatch;
             dequeue_next_frame(expiration_time => max_bcr_delay * C_CLK_PERIOD * 2);