Cleaned code and removed unnecessary assignments

sources/TTCdataEmulator/TTC_Emulator.vhd

@@ -6,7 +6,7 @@
 -- Revised by : Ali Skaf
 -- Email      : ali.skaf@uni-goettingen.de
 -- V2.1: provide OCR and long Bchannel support
--- Last edited; 11.10.2021    
+-- Last edited; 21.10.2021    
 
 --------------------------------------------------------------------------------
 
@@ -106,11 +106,11 @@ architecture Behavioral of TTC_Emulator is
 
     signal      short_b_bchan_valid     : std_logic;
     signal      fifo_bchan_valid        : std_logic;
-    signal      Bch_short_cnt_init      : unsigned(4 downto 0) := "10000";
-    signal      fifo_cnt_init           : unsigned(6 downto 0) := "1000000";
+    constant    Bch_short_cnt_init      : unsigned(4 downto 0) := "10000";
+    constant    fifo_cnt_init           : unsigned(6 downto 0) := "1000000";
 
-    signal      short_bch_cnt           : unsigned(4 downto 0) := "10000";
-    signal      fifo_bch_cnt            : unsigned(6 downto 0) := "1000000";
+    signal      short_bch_cnt           : unsigned(4 downto 0) := Bch_short_cnt_init; --AS: "10000";
+    signal      fifo_bch_cnt            : unsigned(6 downto 0) := fifo_cnt_init ; --AS: "1000000";
     signal      serialization_process   : std_logic := '0';
     signal      Serial_Bchannel         : std_logic := '1';
     signal      Serial_Bchannel_r       : std_logic := '1';
@@ -651,30 +651,20 @@ begin
         sig_out         => fifo_bchan_valid      -- output signal
     );
 
+--FS: For 1 clock delay, we simply push our signals through a single flipflop. 
 
-    short_b_prep_delay: entity work.signal_delay
-    generic map (
-        width     => 1     -- number counter stages used to generate delay given in count_in
-    )
-    port map (
-        clk         => Clock,     -- clock
-        rst         => Reset,     -- sync reset
-        count_in    => (others => '0'),
-        sig_in      => prepare_bcr,     -- input signal
-        sig_out     => prepare_bcr_r      -- delayed output signal
-    );
-
-    short_e_prep_delay: entity work.signal_delay
-    generic map (
-        width     => 1     -- number counter stages used to generate delay given in count_in
-    )
-    port map (
-        clk         => Clock,     -- clock
-        rst         => Reset,     -- sync reset
-        count_in    => (others => '0'),
-        sig_in      => fifo_read,     -- input signal
-        sig_out     => fifo_read_r      -- delayed output signal
-    );
+    process(Clock)
+    begin
+        if rising_edge(Clock) then
+            if Reset = '1' then
+                fifo_read_r <= '0';
+                prepare_bcr_r <= '0';
+            else
+                fifo_read_r <= fifo_read;
+                prepare_bcr_r <= prepare_bcr;
+            end if;
+        end if;
+    end process;
 
     -- Depending on what is triggered, with the shortBchannel for the BCR or the fifo output are registered
     -- The 2 have different lengths
@@ -700,8 +690,8 @@ begin
     begin
         if rising_edge(Clock) then
             if Reset = '1' or user_reset = '1'then
-                Bch_short_cnt_init                  <= "10000";
-                fifo_cnt_init                       <= "1000000";
+                --Bch_short_cnt_init                  <= "10000";
+                --fifo_cnt_init                       <= "1000000";
                 short_b                             <= (others => '1');
                 short_bch_cnt                       <= Bch_short_cnt_init-1;
                 fifo_bch_cnt                        <= fifo_cnt_init-1;
@@ -746,11 +736,6 @@ begin
                         short_bch_cnt               <= Bch_short_cnt_init;
                         fifo_bch_cnt                <= fifo_cnt_init;
                     end if;
-                    Serial_Bchannel                 <= '1';
-                    serialization_process           <= '0';
-                    short_b                         <= (others => '1');
-                    short_bch_cnt                   <= Bch_short_cnt_init;
-                    fifo_bch_cnt                    <= fifo_cnt_init;
                 end if;
        end if;
     end process;
@@ -789,12 +774,6 @@ begin
                         end if;
                  
                     -- INIT STATE  -- AS: Removed as no need to have a specific state for this!
---                    when init =>
---                        if Serial_Bchannel_r = '0' and Serial_Bchannel = '0' then
---                            state <= shortB;
---                        elsif Serial_Bchannel_r = '0' and Serial_Bchannel = '1' then
---                            state <= longB;
---                        end if;
                     
                     --SHORT B STATE
                     when shortB =>