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Commit a2a436ef authored by Frans Schreuder's avatar Frans Schreuder
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Changed LPGBT clock frequency to 240MHz

parent 11bf33e1
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1 merge request!564Resolve FLX-2435 "Phase2/ lpgbt axis clock 240"
Pipeline #7641896 passed
+4
......@@ -408,7 +408,7 @@ package body FELIX_package is
when FIRMWARE_MODE_FELIG_GBT => return 160;
when FIRMWARE_MODE_FMEMU => return 0;
when FIRMWARE_MODE_MROD => return 160;
when FIRMWARE_MODE_LPGBT => return 160;
when FIRMWARE_MODE_LPGBT => return 240;
when FIRMWARE_MODE_INTERLAKEN => return 250; --Using AXI-Stream 64b for Interlaken, this frequency is used for AUX E-Links.
when FIRMWARE_MODE_FELIG_LPGBT => return 160;
when FIRMWARE_MODE_HGTD_LUMI => return 160; -- reducing clock from 240 to 160 for better timing in CRToHost, should be changed back with better timing
......
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