Merge branch 'FLX-1762_AddLicenseHeaders' into phase2/FLX-1762_AddLicenseHeaders

Conflicts:
	simulation/FELIX_Top/felig_sim_top_bnl712.vhd
	simulation/FELIX_Top/waveforms/FELIG_phase1_behav.wcfg
	simulation/ItkStrip/tb_EPROC_OUT4_lcb_phase1.vhd
	simulation/ItkStrip/tb_EPROC_OUT4_r3l1_phase1.vhd
	simulation/ItkStrip/tb_EPROC_OUT8_strips_idle_inserter.vhd
	simulation/ItkStrip/tb_EPROC_OUT8_strips_phase1.vhd
	simulation/ItkStrip/tb_lcb_mux.vhd
	simulation/UVVMExample/tb/FULLModeToHost_tb.vhd
	simulation/Wupper/pcie_ep_sim_model.vhd
	sources/FelixTop/felix_fullmode_top.vhd
	sources/FelixTop/felix_fullmode_top_bnl711.vhd
	sources/FelixTop/felix_top_bnl711.vhd
	sources/GBT/gbt_code/FELIX_gbt_wrapper_KCU.vhd
	sources/ItkStrip/EPROC_OUT4_idle_inserter.vhd
	sources/ItkStrip/EPROC_OUT4_itk_strip_lcb_phase1.vhd
	sources/ItkStrip/EPROC_OUT4_itk_strip_r3l1_phase1.vhd
	sources/ItkStrip/EPROC_OUT8_idle_inserter.vhd
	sources/ItkStrip/EPROC_OUT8_strips_phase1.vhd
	sources/ItkStrip/lcb_mux.vhd
	sources/ItkStrip/lcb_mux_reg.vhd
	sources/ItkStrip/strips_config_map.vhd
	sources/ItkStrip/strips_idle_inserter.vhd
	sources/centralRouter/TTCtoHost_channel.vhd
	sources/centralRouter/thFMdm.vhd
	sources/pcie/dma_read_write.vhd
	sources/templates/dma_control.vhd
	sources/templates/pcie_package.vhd
	sources/templates/strips_config_package.vhd
	sources/templates/strips_config_package.vhd.template
	sources/templates/strips_phase1_long_stave_mapping.vhd
	sources/templates/strips_phase1_long_stave_mapping.vhd.template
	sources/templates/strips_phase1_unknown_mapping.vhd
	sources/templates/strips_phase1_unknown_mapping.vhd.template