FELIG phase-1 into master

Hi @fschreud,

The FELIG phase-1 firmware for the FLX712 is working:

• Fixed some synchronicity issues in the GBT printer that was responsible for some data truncations.
• Implemented the L1 ID reset both for the internal and external trigger, using the register mentioned in the Jira ticket FLX-1410.
• Double the size of one of the generation FIFOs to avoid truncations when using a random trigger.
• A timing constrain was added, and the code is meeting timing.
• FELIG can now be built with different number of channels. Tested for 8, 16 and 24 channels.
• Successfully tested internal and external trigger. The last was a randomly generated trigger created by a TTC system connected to FELIX and then sent to FELIG. ID reset also working as expected.
• A new .coe file was added for the random chunk length option. Working as expected.
• MSB first is working if endianness is changed in FELIG (2-bit and 4-bit elinks only) or if the value of the signal swap_inputbits is changed in FELIX, via register configuration. Although we didn't run the tests you proposed to debug this MSB first problem, we understand the issue well. Looking at the way FELIG is constructed, namely the GBT printer, and what FELIX is expecting, there is no simple solution for this issue. Since we will most likely redo this part of the code for the phase-2 implementation of FELIG, whenever we add the 32-bit elink, we plan to backport it to this version then.
• Lastly, I added some small changes to the read me file. This was because there was no mention to other firmware flavours for phase-1. However, if you think these changes should not be added, feel free to remove then. Please take it as a suggestion.

Overall, I am confident that most of the FELIG issues are now solved. Some features, like direct mode, were not tested because phase-1 FELIX does not support it. The software is in the process of being updated. We are also preparing FELIG documentation. The usage section is already written if you want to take a look.

I merged master into my branch before asking for this request so it should be straight forward. Let me know if you have any questions or comments.

Cheers, Ricardo Edit: Tagging @mtrovato