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fix for 8CH and 12CH Refclks

Merged Marco Trovato requested to merge phase2/master_FLX1496 into phase2/master
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@@ -5,7 +5,8 @@
--! Omega Group --
--!-----------------------------------------------------------------------------
--|
--! author: Kai Chen (kchen@bnl.gov)
--! author: Kai Chen (kchen@bnl.gov)
--! modified by: Marco Trovato (mtrovato@anl.gov)
--!
--!
--!-----------------------------------------------------------------------------
@@ -358,11 +359,6 @@ or ((12 < GBT_NUM) and (GBT_NUM <= 24) and (FE_EMU_EN = 1) and (CLK_CHIP_SEL = 1
end generate g_refclk_48ch;
g_refclk_48ch_sel1: if ((24 < GBT_NUM) and (GBT_NUM <= 48) and (FE_EMU_EN = 0) and (CLK_CHIP_SEL = 1)) generate
GTH_REFCLK_OUT(GBT_NUM-1 downto 0) <= GTH_RefClk(GBT_NUM-1 downto 0);
GTH_EMU_REFCLK_OUT <= (others=>'0');
end generate;
g_refclk_48ch_sel2: if ((12 < GBT_NUM) and (GBT_NUM <= 24) and (FE_EMU_EN = 1) and (CLK_CHIP_SEL = 1)) generate
GTH_REFCLK_OUT(GBT_NUM-1 downto 0) <= GTH_RefClk(GBT_NUM-1 downto 0);
GTH_EMU_REFCLK_OUT(GBT_NUM-1 downto 0) <= GTH_RefClk(GBT_NUM+23 downto 24);
@@ -398,39 +394,44 @@ or ((6 < GBT_NUM) and (GBT_NUM <= 12) and (FE_EMU_EN = 1) and (CLK_CHIP_SEL = 1)
GTH_RefClk(23) <= LMK2_REFCLK;
end generate g_refclk_24ch;
g_refclk_24ch_sel1: if ((12 < GBT_NUM) and (GBT_NUM <= 24) and (FE_EMU_EN = 0) and (CLK_CHIP_SEL = 1)) generate
GTH_REFCLK_OUT(GBT_NUM-1 downto 0) <= GTH_RefClk(GBT_NUM-1 downto 0);
GTH_EMU_REFCLK_OUT <= (others=>'0');
end generate;
g_refclk_24ch_sel2: if ((6 < GBT_NUM) and (GBT_NUM <= 12) and (FE_EMU_EN = 1) and (CLK_CHIP_SEL = 1)) generate
GTH_REFCLK_OUT(GBT_NUM-1 downto 0) <= GTH_RefClk(GBT_NUM-1 downto 0);
GTH_EMU_REFCLK_OUT(GBT_NUM-1 downto 0) <= GTH_RefClk(GBT_NUM+11 downto 12);
end generate;
--MT added case with <=12 GBT_NUM, CLK_CHIP_SEL=1 and FE_EMU_EN=0
g_refclk_12ch: if ( (GBT_NUM <= 12) and (FE_EMU_EN = 0) and (CLK_CHIP_SEL = 1) ) generate
g_refclk_12ch: if ( (8 < GBT_NUM) and (GBT_NUM <= 12) and (FE_EMU_EN = 0) and (CLK_CHIP_SEL = 1) ) generate
GTH_RefClk( 0) <= LMK1_REFCLK;
GTH_RefClk( 1) <= LMK1_REFCLK;
GTH_RefClk( 2) <= LMK1_REFCLK;
GTH_RefClk( 3) <= LMK1_REFCLK;
GTH_RefClk( 4) <= LMK1_REFCLK;
GTH_RefClk( 5) <= LMK1_REFCLK;
GTH_RefClk( 6) <= LMK1_REFCLK;
GTH_RefClk( 7) <= LMK1_REFCLK;
GTH_RefClk( 8) <= LMK0_REFCLK;
GTH_RefClk( 9) <= LMK0_REFCLK;
GTH_RefClk(10) <= LMK0_REFCLK;
GTH_RefClk(11) <= LMK0_REFCLK;
GTH_RefClk( 4) <= LMK1_REFCLK;
GTH_RefClk( 5) <= LMK1_REFCLK;
GTH_RefClk( 6) <= LMK1_REFCLK;
GTH_RefClk( 7) <= LMK1_REFCLK;
GTH_RefClk( 8) <= LMK3_REFCLK;
GTH_RefClk( 9) <= LMK3_REFCLK;
GTH_RefClk(10) <= LMK3_REFCLK;
GTH_RefClk(11) <= LMK3_REFCLK;
end generate g_refclk_12ch;
g_refclk_8ch: if ( (GBT_NUM <= 8) and (FE_EMU_EN = 0) and (CLK_CHIP_SEL = 1) ) generate
GTH_RefClk( 0) <= LMK1_REFCLK;
GTH_RefClk( 1) <= LMK1_REFCLK;
GTH_RefClk( 2) <= LMK1_REFCLK;
GTH_RefClk( 3) <= LMK1_REFCLK;
GTH_RefClk( 4) <= LMK3_REFCLK;
GTH_RefClk( 5) <= LMK3_REFCLK;
GTH_RefClk( 6) <= LMK3_REFCLK;
GTH_RefClk( 7) <= LMK3_REFCLK;
end generate g_refclk_8ch;
g_refclk_12ch_sel1: if ((GBT_NUM <= 12) and (FE_EMU_EN = 0) and (CLK_CHIP_SEL = 1)) generate
GTH_REFCLK_OUT(GBT_NUM-1 downto 0) <= GTH_RefClk(GBT_NUM-1 downto 0);
GTH_EMU_REFCLK_OUT <= (others=>'0');
end generate;
--
@@ -489,10 +490,6 @@ g_refclk_48ch_SI: if ((24 < GBT_NUM) and (GBT_NUM <= 48) and (FE_EMU_EN = 0) and
end generate g_refclk_48ch_SI;
g_refclk_48ch_SI_sel1: if ((24 < GBT_NUM) and (GBT_NUM <= 48) and (FE_EMU_EN = 0) and (CLK_CHIP_SEL = 0)) generate
GTH_REFCLK_OUT(GBT_NUM-1 downto 0) <= GTH_RefClk(GBT_NUM-1 downto 0);
GTH_EMU_REFCLK_OUT <= (others=>'0');
end generate;
g_refclk_48ch_SI_sel2: if ((12 < GBT_NUM) and (GBT_NUM <= 24) and (FE_EMU_EN = 1) and (CLK_CHIP_SEL = 0)) generate
GTH_REFCLK_OUT(GBT_NUM-1 downto 0) <= GTH_RefClk(GBT_NUM-1 downto 0);
GTH_EMU_REFCLK_OUT(GBT_NUM-1 downto 0) <= GTH_RefClk(GBT_NUM+23 downto 24);
@@ -528,18 +525,13 @@ or ((6 < GBT_NUM) and (GBT_NUM <= 12) and (FE_EMU_EN = 1) and (CLK_CHIP_SEL = 0)
GTH_RefClk(23) <= SI2_REFCLK;
end generate g_refclk_24ch_SI;
g_refclk_24ch_SI_sel1: if ((12 < GBT_NUM) and (GBT_NUM <= 24) and (FE_EMU_EN = 0) and (CLK_CHIP_SEL = 0)) generate
GTH_REFCLK_OUT(GBT_NUM-1 downto 0) <= GTH_RefClk(GBT_NUM-1 downto 0);
GTH_EMU_REFCLK_OUT <= (others=>'0');
end generate;
g_refclk_24ch_SI_sel2: if ((6 < GBT_NUM) and (GBT_NUM <= 12) and (FE_EMU_EN = 1) and (CLK_CHIP_SEL = 0)) generate
GTH_REFCLK_OUT(GBT_NUM-1 downto 0) <= GTH_RefClk(GBT_NUM-1 downto 0);
GTH_EMU_REFCLK_OUT(GBT_NUM-1 downto 0) <= GTH_RefClk(GBT_NUM+11 downto 12);
end generate;
--MT added case with <=12 GBT_NUM, CLK_CHIP_SEL=0, FE_EMU_EN=0
g_refclk_12ch_SI: if ( (GBT_NUM <= 12) and (FE_EMU_EN = 0) and (CLK_CHIP_SEL = 0)) generate
g_refclk_12ch_SI: if ( (8 < GBT_NUM) and (GBT_NUM <= 12) and (FE_EMU_EN = 0) and (CLK_CHIP_SEL = 0)) generate
GTH_RefClk( 0) <= SI0_REFCLK;
GTH_RefClk( 1) <= SI0_REFCLK;
@@ -549,14 +541,27 @@ g_refclk_12ch_SI: if ( (GBT_NUM <= 12) and (FE_EMU_EN = 0) and (CLK_CHIP_SEL = 0
GTH_RefClk( 5) <= SI0_REFCLK;
GTH_RefClk( 6) <= SI0_REFCLK;
GTH_RefClk( 7) <= SI0_REFCLK;
GTH_RefClk( 8) <= SI0_REFCLK;
GTH_RefClk( 9) <= SI0_REFCLK;
GTH_RefClk(10) <= SI0_REFCLK;
GTH_RefClk(11) <= SI0_REFCLK;
GTH_RefClk( 8) <= SI2_REFCLK;
GTH_RefClk( 9) <= SI2_REFCLK;
GTH_RefClk(10) <= SI2_REFCLK;
GTH_RefClk(11) <= SI2_REFCLK;
end generate g_refclk_12ch_SI;
g_refclk_12ch_SI_sel1: if ( (GBT_NUM <= 12) and (FE_EMU_EN = 0) and (CLK_CHIP_SEL = 0) ) generate
g_refclk_8ch_SI: if ( (GBT_NUM <= 8) and (FE_EMU_EN = 0) and (CLK_CHIP_SEL = 0)) generate
GTH_RefClk( 0) <= SI0_REFCLK;
GTH_RefClk( 1) <= SI0_REFCLK;
GTH_RefClk( 2) <= SI0_REFCLK;
GTH_RefClk( 3) <= SI0_REFCLK;
GTH_RefClk( 4) <= SI2_REFCLK;
GTH_RefClk( 5) <= SI2_REFCLK;
GTH_RefClk( 6) <= SI2_REFCLK;
GTH_RefClk( 7) <= SI2_REFCLK;
end generate g_refclk_8ch_SI;
g_refclk_sel1: if ( (GBT_NUM <= 48) and (FE_EMU_EN = 0) ) generate
GTH_REFCLK_OUT(GBT_NUM-1 downto 0) <= GTH_RefClk(GBT_NUM-1 downto 0);
GTH_EMU_REFCLK_OUT <= (others=>'0');
end generate;
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