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Resolve FLX-1543 "Felig"

Ricardo Luz requested to merge FLX-1543_felig into master

Hi @fschreud

Here is the merge request we talked about this morning. The main change is the routing of an input clock to the SI (see issue FLX-1543). Marco also pointed out a small bug in one of the IPs that I fixed in this branch.

If the tests show that the changes solve the alignment issues, you can go ahead and merge.

Cheers, Ricardo

ps: tagging @mtrovato and @paramon

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