The toplevel VHDL files for BNL712 did not have the Si5345_RSTN pin, this was...

Frans Schreuderrequested to merge
FLX-1707_SI5345RstPin into master

The toplevel VHDL files for BNL712 did not have the Si5345_RSTN pin, this was added now. For FLX712 constraints, the correct pin was added, for BNL711 constraints (v1.5) a dummy pin was assigned

Closes FLX-1707

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