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FLX-1765: Implemented dynamic selection of DMA descriptor based on AXIS_ID

Merged FLX-1765: Implemented dynamic selection of DMA descriptor based on AXIS_ID
phase2/FLX-1765_CRToHost_Configurable_DMA_Channel into phase2/master
Merged Frans Schreuder requested to merge phase2/FLX-1765_CRToHost_Configurable_DMA_Channel into phase2/master
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simulation/UVVMtests/tb/FULLModeToHost_tb.vhd
+ 50
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@@ -137,6 +137,9 @@ architecture arch of FULLModeToHost_tb is
@@ -137,6 +137,9 @@ architecture arch of FULLModeToHost_tb is
trigger_type => x"0000",
trigger_type => x"0000",
data_rdy => '0'
data_rdy => '0'
);
);
 
signal CRTOHOST_DMA_DESCRIPTOR_WREN : std_logic_vector(0 downto 0);
 
signal CRTOHOST_DMA_DESCRIPTOR_DESCR : std_logic_vector(2 downto 0);
 
signal CRTOHOST_DMA_DESCRIPTOR_AXIS_ID : std_logic_vector(10 downto 0);
begin
begin
LinkAligned <= (others => '0');
LinkAligned <= (others => '0');
@@ -180,6 +183,53 @@ begin
@@ -180,6 +183,53 @@ begin
register_map_40_control.FE_EMU_CONFIG.WRDATA <= (others => '0');
register_map_40_control.FE_EMU_CONFIG.WRDATA <= (others => '0');
register_map_40_control.GBT_TOHOST_FANOUT.SEL <= (others => '1');
register_map_40_control.GBT_TOHOST_FANOUT.SEL <= (others => '1');
register_map_control_appreg_clk <= register_map_40_control;
register_map_control_appreg_clk <= register_map_40_control;
 
register_map_40_control.CRTOHOST_DMA_DESCRIPTOR_1.WR_EN <= CRTOHOST_DMA_DESCRIPTOR_WREN;
 
register_map_40_control.CRTOHOST_DMA_DESCRIPTOR_1.DESCR <= CRTOHOST_DMA_DESCRIPTOR_DESCR;
 
register_map_40_control.CRTOHOST_DMA_DESCRIPTOR_2.AXIS_ID <= CRTOHOST_DMA_DESCRIPTOR_AXIS_ID;
 
associate_epath_id: process
 
begin
 
wait until falling_edge(reset);
 
wait for C_CLK40_PERIOD*10;
 
CRTOHOST_DMA_DESCRIPTOR_WREN <= "1";
 
CRTOHOST_DMA_DESCRIPTOR_AXIS_ID <= "00000000000";
 
CRTOHOST_DMA_DESCRIPTOR_DESCR <= "000";
 
wait for C_CLK40_PERIOD;
 
CRTOHOST_DMA_DESCRIPTOR_AXIS_ID <= "00001000000";
 
CRTOHOST_DMA_DESCRIPTOR_DESCR <= "001";
 
wait for C_CLK40_PERIOD;
 
CRTOHOST_DMA_DESCRIPTOR_AXIS_ID <= "00010000000";
 
CRTOHOST_DMA_DESCRIPTOR_DESCR <= "010";
 
wait for C_CLK40_PERIOD;
 
CRTOHOST_DMA_DESCRIPTOR_AXIS_ID <= "00011000000";
 
CRTOHOST_DMA_DESCRIPTOR_DESCR <= "011";
 
wait for C_CLK40_PERIOD;
 
CRTOHOST_DMA_DESCRIPTOR_AXIS_ID <= "00100000000";
 
CRTOHOST_DMA_DESCRIPTOR_DESCR <= "000";
 
wait for C_CLK40_PERIOD;
 
CRTOHOST_DMA_DESCRIPTOR_AXIS_ID <= "00101000000";
 
CRTOHOST_DMA_DESCRIPTOR_DESCR <= "001";
 
wait for C_CLK40_PERIOD;
 
CRTOHOST_DMA_DESCRIPTOR_AXIS_ID <= "00110000000";
 
CRTOHOST_DMA_DESCRIPTOR_DESCR <= "010";
 
wait for C_CLK40_PERIOD;
 
CRTOHOST_DMA_DESCRIPTOR_AXIS_ID <= "00111000000";
 
CRTOHOST_DMA_DESCRIPTOR_DESCR <= "011";
 
wait for C_CLK40_PERIOD;
 
CRTOHOST_DMA_DESCRIPTOR_AXIS_ID <= "01000000000";
 
CRTOHOST_DMA_DESCRIPTOR_DESCR <= "000";
 
wait for C_CLK40_PERIOD;
 
CRTOHOST_DMA_DESCRIPTOR_AXIS_ID <= "01001000000";
 
CRTOHOST_DMA_DESCRIPTOR_DESCR <= "001";
 
wait for C_CLK40_PERIOD;
 
CRTOHOST_DMA_DESCRIPTOR_AXIS_ID <= "01010000000";
 
CRTOHOST_DMA_DESCRIPTOR_DESCR <= "010";
 
wait for C_CLK40_PERIOD;
 
CRTOHOST_DMA_DESCRIPTOR_AXIS_ID <= "01011000000";
 
CRTOHOST_DMA_DESCRIPTOR_DESCR <= "011";
 
wait for C_CLK40_PERIOD;
 
CRTOHOST_DMA_DESCRIPTOR_WREN <= "0";
 
wait;
 
end process;
g_NogbtEmu: if FIRMWARE_MODE /= FIRMWARE_MODE_GBT generate
g_NogbtEmu: if FIRMWARE_MODE /= FIRMWARE_MODE_GBT generate
LinkAligned_FOSEL <= LinkAligned(((GBT_NUM/ENDPOINTS)*(pcie_endpoint+1))-1 downto (GBT_NUM/ENDPOINTS)*pcie_endpoint);
LinkAligned_FOSEL <= LinkAligned(((GBT_NUM/ENDPOINTS)*(pcie_endpoint+1))-1 downto (GBT_NUM/ENDPOINTS)*pcie_endpoint);