Resolve FLX-2440 "Phase2/ flx182 constraints"

Closes FLX-2440

assigned to @fschreud

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• e8f181ec - Added CARD_TYPE to ltittc_tb.vhd, removed some old IP cores

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• 514537b1 - Removed obsolete VHDL files

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• 807aee52 - Revoved some non-standard packages
• d2e47433 - Shared IBUFDS_GTE5 between LTI (refclk1) and transceiver quad 201 refclk1 for...

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• fe1bcd01 - Removed unconnected ODIV2 outputs from versal LTITTC transceiver. Not yet used...

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• 0f054bf5 - Changed BUFG_GT to BUFGCE_DIV in LTI block design

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• b8e19645 - Removed FELIG function_lib which containted only one function, also available...

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• 96286282 - Adjusted number of LTI inputs for FLX182 (and allow sharing refclk with quad0 of transceivers)

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• aa29a37b - Adjusted number of LTI inputs for FLX182 (and allow sharing refclk with quad0 of transceivers)

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• ee27ddac - Use bank 201 for LTI refclk1 (was 202 for some reason)

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• 56123bc2 - Added LOC constraints for lpGBT transceiver IBUFDS_GTE5

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• d48e267e - Added build script for 20ch strip (FLX182)

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• 55e97aa3 - set deterministic build time to false to retry with a different timestamp
• 8bafcc1e - Imported cips_bd_BNL182 and transceiver_versal_LTITTC again from FLX-1216...

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• 9478c7c6 - Imported cips_bd_BNL182 and transceiver_versal_LTITTC again from FLX-1216...

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• 4c79cc6e - Reorganized GTH/GTY RX transceiver signals in LTITTC link wrapper

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• fb3a7d08 - Timing constraints for LTI transceiver refclk and default value for BUFGCE_CLR

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• 9bd03020 - Added some e-links in FLX182 full mode
• a0f1be69 - Merge branch 'phase2/release-5.2' into phase2/FLX-2440_FLX182_constraints

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• ad339927 - disable src_input_reg for busy XPM_CDC
• 35b2f055 - Merge remote-tracking branch 'origin/phase2/FLX-2440_FLX182_constraints' into phase2/release-5.2
• 1cf37982 - Updated create_generated_clock constraint

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• aae43533 - Route TXUSRCLK_LTI to SMA 4/5

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• 6794ed08 - fixed typo

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