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Resolve FLX-2440 "Phase2/ flx182 constraints"

Merged Resolve FLX-2440 "Phase2/ flx182 constraints"
phase2/FLX-2440_FLX182_constraints into phase2/master
Merged Frans Schreuder requested to merge phase2/FLX-2440_FLX182_constraints into phase2/master
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26
constraints/felix_top_FLX182.xdc
+ 23
− 3
@@ -166,8 +166,13 @@ set_property PACKAGE_PIN AC9 [get_ports {TX_P_LTITTC[3]}]
set_property PACKAGE_PIN AC8 [get_ports {TX_N_LTITTC[3]}]
set_property PACKAGE_PIN AC4 [get_ports {RX_P_LTITTC[3]}]
set_property PACKAGE_PIN AC3 [get_ports {RX_N_LTITTC[3]}]
create_clock -period 6.400 [get_ports {GTREFCLK0_LTITTC_P[0]}]
#set_property -quiet CH0_EYESCAN_CFG0 32'h01800000 [get_cells TTCLTI.ltittc0/u2/g_TTC_182.GTY_LTITTCLINK_TOP_INST/transceiver_versal_LTITTC_i]
set_property -quiet LOC GTY_REFCLK_X1Y3 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_FLX182_Not_Interlaken.IBUFDS_GTE5_REF1"}]
set_property -quiet LOC GTY_REFCLK_X1Y1 [get_cells -hierarchical -filter {NAME =~ "TTCLTI.ltittc0/u2/g_TTC_182.GTY_LTITTCLINK_TOP_INST/*/USE_IBUFDS_GTE5.GEN_IBUFDS_GTE5[0].IBUFDS_GTE5_I"}]
create_generated_clock -name clk40_lti -source [get_pins -hierarchical -filter {NAME =~ "TTCLTI.ltittc0/u2/g_TTC_182.GTY_LTITTCLINK_TOP_INST/*/USE_BUFGCE_DIV2.GEN_BUFGCE_DIV2[0].BUFGCE_DIV2_I/I"}] -divide_by 6 [get_pins -hierarchical -filter {NAME =~ "TTCLTI.ltittc0/u2/g_TTC_182.GTY_LTITTCLINK_TOP_INST/*/USE_BUFGCE_DIV2.GEN_BUFGCE_DIV2[0].BUFGCE_DIV2_I/O"}]
set_property -quiet LOC GTY_REFCLK_X1Y1 [get_cells -hierarchical -filter {NAME =~ "TTCLTI.ltittc0/u2/g_TTC_182.GTY_LTITTCLINK_TOP_INST/transceiver_versal_LTITTC_i/util_ds_buf/U0/USE_IBUFDS_GTE5.GEN_IBUFDS_GTE5[0].IBUFDS_GTE5_I"}]
#Bank 201
set_property PACKAGE_PIN AB11 [get_ports {GTREFCLK_P_IN[0]}]
@@ -175,9 +180,9 @@ set_property PACKAGE_PIN AB11 [get_ports {GTREFCLK_P_IN[0]}]
set_property -quiet LOC GTY_REFCLK_X1Y2 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_INTERLAKEN.il0/g_quads[0].g_versalprime.IBUFDS_GTE5_REF0"}]
set_property -quiet LOC GTY_REFCLK_X1Y3 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_INTERLAKEN.il0/g_quads[0].g_versalprime.IBUFDS_GTE5_REF1"}]
set_property -quiet LOC GTY_REFCLK_X1Y2 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_FULLMODE.u2/g_versal.g_versal_quads[0]*.IBUFDS_GTE5_I"}]
set_property -quiet LOC GTY_REFCLK_X1Y2 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_GBTMODE.g_versal.u2/GTH_inst[0]*.IBUFDS_GTE5_I"}]
set_property -quiet LOC GTY_REFCLK_X1Y2 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[0]*.IBUFDS_GTE5_I"}]
set_property -quiet PACKAGE_PIN M15 [get_ports {GTREFCLK1_P_IN[0]}]
set_property -quiet LOC GTY_REFCLK_X1Y5 [get_cells TTCLTI.ltittc0/u2/g_TTC_182.GTY_LTITTCLINK_TOP_INST/transceiver_versal_LTITTC_i/util_ds_buf_0/U0/USE_IBUFDS_GTE5.GEN_IBUFDS_GTE5[0].IBUFDS_GTE5_I]
set_property -quiet CH0_EYESCAN_CFG0 32'h01800000 [get_cells TTCLTI.ltittc0/u2/g_TTC_182.GTY_LTITTCLINK_TOP_INST/transceiver_versal_LTITTC_i]
set_property PACKAGE_PIN AB2 [get_ports {RX_P[0]}]
set_property PACKAGE_PIN AA4 [get_ports {RX_P[1]}]
@@ -188,6 +193,9 @@ set_property -quiet PACKAGE_PIN L13 [get_ports {GTREFCLK_P_IN[1]}]
set_property -quiet LOC GTY_REFCLK_X1Y4 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_INTERLAKEN.il0/g_quads[1].g_versalprime.IBUFDS_GTE5_REF0"}]
set_property -quiet LOC GTY_REFCLK_X1Y5 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_INTERLAKEN.il0/g_quads[1].g_versalprime.IBUFDS_GTE5_REF1"}]
set_property -quiet LOC GTY_REFCLK_X1Y4 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_FULLMODE.u2/g_versal.g_versal_quads[1]*.IBUFDS_GTE5_I"}]
set_property -quiet LOC GTY_REFCLK_X1Y4 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_GBTMODE.g_versal.u2/GTH_inst[1]*.IBUFDS_GTE5_I"}]
set_property -quiet LOC GTY_REFCLK_X1Y4 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[1]*.IBUFDS_GTE5_I"}]
set_property -quiet PACKAGE_PIN K15 [get_ports {GTREFCLK1_P_IN[1]}]
set_property -quiet PACKAGE_PIN V2 [get_ports {RX_P[4]}]
set_property -quiet PACKAGE_PIN U4 [get_ports {RX_P[5]}]
@@ -199,6 +207,9 @@ set_property -quiet PACKAGE_PIN H15 [get_ports {GTREFCLK1_P_IN[2]}]
set_property -quiet LOC GTY_REFCLK_X1Y6 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_INTERLAKEN.il0/g_quads[2].g_versalprime.IBUFDS_GTE5_REF0"}]
set_property -quiet LOC GTY_REFCLK_X1Y7 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_INTERLAKEN.il0/g_quads[2].g_versalprime.IBUFDS_GTE5_REF1"}]
set_property -quiet LOC GTY_REFCLK_X1Y6 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_FULLMODE.u2/g_versal.g_versal_quads[2]*.IBUFDS_GTE5_I"}]
set_property -quiet LOC GTY_REFCLK_X1Y6 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_GBTMODE.g_versal.u2/GTH_inst[2]*.IBUFDS_GTE5_I"}]
set_property -quiet LOC GTY_REFCLK_X1Y6 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[2]*.IBUFDS_GTE5_I"}]
set_property -quiet PACKAGE_PIN P2 [get_ports {RX_P[8]}]
set_property -quiet PACKAGE_PIN N4 [get_ports {RX_P[9]}]
set_property -quiet PACKAGE_PIN M2 [get_ports {RX_P[10]}]
@@ -209,6 +220,9 @@ set_property -quiet PACKAGE_PIN F15 [get_ports {GTREFCLK1_P_IN[3]}]
set_property -quiet LOC GTY_REFCLK_X1Y8 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_INTERLAKEN.il0/g_quads[3].g_versalprime.IBUFDS_GTE5_REF0"}]
set_property -quiet LOC GTY_REFCLK_X1Y9 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_INTERLAKEN.il0/g_quads[3].g_versalprime.IBUFDS_GTE5_REF1"}]
set_property -quiet LOC GTY_REFCLK_X1Y8 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_FULLMODE.u2/g_versal.g_versal_quads[3]*.IBUFDS_GTE5_I"}]
set_property -quiet LOC GTY_REFCLK_X1Y8 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_GBTMODE.g_versal.u2/GTH_inst[3]*.IBUFDS_GTE5_I"}]
set_property -quiet LOC GTY_REFCLK_X1Y8 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[3]*.IBUFDS_GTE5_I"}]
set_property -quiet PACKAGE_PIN K2 [get_ports {RX_P[12]}]
set_property -quiet PACKAGE_PIN J4 [get_ports {RX_P[13]}]
set_property -quiet PACKAGE_PIN H2 [get_ports {RX_P[14]}]
@@ -219,6 +233,9 @@ set_property -quiet PACKAGE_PIN D15 [get_ports {GTREFCLK1_P_IN[4]}]
set_property -quiet LOC GTY_REFCLK_X1Y10 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_INTERLAKEN.il0/g_quads[4].g_versalprime.IBUFDS_GTE5_REF0"}]
set_property -quiet LOC GTY_REFCLK_X1Y11 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_INTERLAKEN.il0/g_quads[4].g_versalprime.IBUFDS_GTE5_REF1"}]
set_property -quiet LOC GTY_REFCLK_X1Y10 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_FULLMODE.u2/g_versal.g_versal_quads[4]*.IBUFDS_GTE5_I"}]
set_property -quiet LOC GTY_REFCLK_X1Y10 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_GBTMODE.g_versal.u2/GTH_inst[4]*.IBUFDS_GTE5_I"}]
set_property -quiet LOC GTY_REFCLK_X1Y10 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[4]*.IBUFDS_GTE5_I"}]
set_property -quiet PACKAGE_PIN G4 [get_ports {RX_P[16]}]
set_property -quiet PACKAGE_PIN F2 [get_ports {RX_P[17]}]
set_property -quiet PACKAGE_PIN F6 [get_ports {RX_P[18]}]
@@ -229,6 +246,9 @@ set_property -quiet PACKAGE_PIN B15 [get_ports {GTREFCLK1_P_IN[5]}]
set_property -quiet LOC GTY_REFCLK_X1Y12 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_INTERLAKEN.il0/g_quads[5].g_versalprime.IBUFDS_GTE5_REF0"}]
set_property -quiet LOC GTY_REFCLK_X1Y13 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_INTERLAKEN.il0/g_quads[5].g_versalprime.IBUFDS_GTE5_REF1"}]
set_property -quiet LOC GTY_REFCLK_X1Y12 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_FULLMODE.u2/g_versal.g_versal_quads[5]*.IBUFDS_GTE5_I"}]
set_property -quiet LOC GTY_REFCLK_X1Y12 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_GBTMODE.g_versal.u2/GTH_inst[5]*.IBUFDS_GTE5_I"}]
set_property -quiet LOC GTY_REFCLK_X1Y12 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_LPGBTMODE.u2/FLX_LpGBT_BE_INST/GTH_inst[5]*.IBUFDS_GTE5_I"}]
set_property -quiet PACKAGE_PIN D2 [get_ports {RX_P[20]}]
set_property -quiet PACKAGE_PIN D6 [get_ports {RX_P[21]}]
set_property -quiet PACKAGE_PIN C4 [get_ports {RX_P[22]}]