Resolve FLX-2440 "Phase2/ flx182 constraints"

Closes FLX-2440

sources/FelixTop/felix_top.vhd

@@ -403,6 +403,7 @@ architecture structure of felix_top is
     signal apb3_axi_clk : std_logic;
     signal LTI2cips_gpio : std_logic_vector(3 downto 0);
     signal cips2LTI_gpio: std_logic_vector(3 downto 0);
+    signal LTI_TXUSRCLK_out: std_logic;
 
 begin
 
@@ -424,11 +425,11 @@ begin
                 OB=> SmaOut(2)
             );
 
-    --SmaObuff2: OBUFDS port map(
-    --        I=> LTI_TXUSRCLK_lti_up,
-    --        O=> SmaOut(5),
-    --        OB=> SmaOut(4)
-    --    );
+        SmaObuff2: OBUFDS port map(
+                I=> LTI_TXUSRCLK_out,
+                O=> SmaOut(5),
+                OB=> SmaOut(4)
+            );
     end generate;
     I2C_nRESET_PCIe <= (others => '1');
     uC_reset_N <= (others => '1');
@@ -1331,6 +1332,7 @@ begin
                 TX_P_LTITTC                    => TX_P_LTITTC(0),
                 TX_N_LTITTC                    => TX_N_LTITTC(0),
                 RXUSRCLK_LTI                   => RXUSRCLK_LTI,
+                TXUSRCLK_LTI                   => TXUSRCLK_LTI_out,
                 axi_clk_in => apb3_axi_clk,
                 axi_miso_ttc_lti => axi_miso_ttc_lti,
                 axi_mosi_ttc_lti => axi_mosi_ttc_lti,