Resolve FLX-2440 "Phase2/ flx182 constraints"

Closes FLX-2440

constraints/felix_top_FLX182.xdc

@@ -166,11 +166,14 @@ set_property PACKAGE_PIN AC9 [get_ports {TX_P_LTITTC[3]}]
 set_property PACKAGE_PIN AC8 [get_ports {TX_N_LTITTC[3]}]
 set_property PACKAGE_PIN AC4 [get_ports {RX_P_LTITTC[3]}]
 set_property PACKAGE_PIN AC3 [get_ports {RX_N_LTITTC[3]}]
-
+create_clock -name LTIREFCLK_156_25 -period 6.400 [get_ports {GTREFCLK0_LTITTC_P[0]}]
 #set_property -quiet CH0_EYESCAN_CFG0 32'h01800000 [get_cells TTCLTI.ltittc0/u2/g_TTC_182.GTY_LTITTCLINK_TOP_INST/transceiver_versal_LTITTC_i]
 set_property -quiet LOC GTY_REFCLK_X1Y3 [get_cells -hierarchical -filter {NAME =~ "linkwrapper0/g_FLX182_Not_Interlaken.IBUFDS_GTE5_REF1"}]
 set_property -quiet LOC GTY_REFCLK_X1Y1 [get_cells -hierarchical -filter {NAME =~ "TTCLTI.ltittc0/u2/g_TTC_182.GTY_LTITTCLINK_TOP_INST/*/USE_IBUFDS_GTE5.GEN_IBUFDS_GTE5[0].IBUFDS_GTE5_I"}]
 
+create_generated_clock -name clk40_lti -add -master_clock [get_clocks -of_objects [get_pins TTCLTI.ltittc0/u2/g_TTC_182.GTY_LTITTCLINK_TOP_INST/transceiver_versal_LTITTC_i/transceiver_versal_LTITTC_i/util_ds_buf1/BUFGCE_I]] -source [get_pins -hierarchical -filter {NAME =~ "TTCLTI.ltittc0/u2/g_TTC_182.GTY_LTITTCLINK_TOP_INST/*/USE_BUFGCE_DIV2.GEN_BUFGCE_DIV2[0].BUFGCE_DIV2_I/I"}] -divide_by 6 [get_pins -hierarchical -filter {NAME =~ "TTCLTI.ltittc0/u2/g_TTC_182.GTY_LTITTCLINK_TOP_INST/*/USE_BUFGCE_DIV2.GEN_BUFGCE_DIV2[0].BUFGCE_DIV2_I/O"}]
+
+
 #Bank 201
 set_property PACKAGE_PIN AB11 [get_ports {GTREFCLK_P_IN[0]}]
 #TODO: set LOC for different transceiver modes: