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Created with Raphaël 2.2.014Mar1110987432128Feb252423221918171615141312111098732128Jan272017151413121110929Dec2322212017161514131110987632130Nov292625242319181716121198121Oct15141211987654129Sep242322212017161487632131Aug30292726252423201918171613121110986543229Jul2725232220191615141312987653230Jun282725242018161511987HDLC encoder can transform single-byte frames (consisting of the 0xFF byte) into a fixed idle timeupdating lpgbt-fpga to last commitMerge remote-tracking branch 'origin/FLX-1631_configurable-regmap-multi' into phase2/FLX-1849_removeregisters_for_firmware_modesAdded possibility in WuppercodeGen to eliminate 2D arrays for certain fw_modes (mostly FEI4 configuration registers are now removed)connected RXUSRCLK to housekeepingmerge conflicts fixesSelected registers to eliminate for certain modes. Need to figure out how to do 2D arraysTCL is very sensitive for whitespace...Fixed typo in scriptFixed Loopback25G_tb after phase2/master mergeMerge branch 'phase2/FLX-1769_AddGBTForVCU128' of ssh://gitlab.cern.ch:7999/atlas-tdaq-felix/firmware into phase2/FLX-1769_AddGBTForVCU128Merge branch 'FLX-1631_configurable-regmap-multi' of ssh://gitlab.cern.ch:7999/atlas-tdaq-felix/firmware into FLX-1631_configurable-regmap-multiAutomatically enable firmware specific dma_control.vhd in do_implementation_post scriptAdded generated dma_control_N.vhd files for different firmware modesGenerated filesTake WupperCodeGen from master, change some whitespace in dma_control.vhd.templateMerge remote-tracking branch 'origin/phase2/master' into FLX-1631_configurable-regmap-multiMerge remote-tracking branch 'origin/phase2/master' into phase2/FLX-1769_AddGBTForVCU128Removed data_width_package_256 from itk_strips_fileset.tcl removed axis_noc.bd import from scriptsRenamed sys_reset_n to PCIE_PERSTn in toplevel and pcie_ep_wrapEndpoints changed to two. FLX-1831regenerated Versal BNL181 .bd files for PCIe from example designtiming fixes in interlaken_gtyRemoved unnecessary clock group constraints for VCU128Added reset synchronization in CRFromHost (25Gb/s LINK_CONFIG)Removed USE_NOC from CRToHost and felix_topFixed duplicate driver on wr_data_count in xpm_uram_fifo_async, removed NoC support in CRToHostdm, it doesn't help much anyway and doesn't support dynamic routing which is needed now.Merge branch 'phase2/FLX-1835_AdjustBUSYWaterMarks' into 'phase2/master'Some changes in core1990_interlakenSome fixes in core1990_interlaken (see branch SmallFix), Added connections to Si5345 on FELIX 25G MezzanineMerge branch 'phase2/FLX-1769_AddGBTForVCU128' of ssh://gitlab.cern.ch:7999/atlas-tdaq-felix/firmware into phase2/FLX-1769_AddGBTForVCU128Fixed testbenches and wupper_oc_top after moving tohostfifo_wr_data_count into WupperFifosMerge branch 'thea/fm_halfrate_rx_linerate_fix' into dune/developdune/v1.1.1 dun…dune/v1.1.1 dune/developsmall fix to LaneRegisterRemapper.vhdMoved BUSY for the Wupper FIFO into WupperFifos (was in CRToHost) and fixed that it worked only for fifo 0Updated Core1990 to master branchMerge branch 'phase2/FLX-1821_ChannelFifoSize' into 'phase2/master'Merge branch 'rm-4.11_version' into 'master'Fixed some issues regarding reference clocks for VU37PIncreased channel fifo size for all flavours, but depending on flavour was 2kB deep, now: GBT: 4kB, all other: 16kB