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Created with Raphaël 2.2.029Mar252423222118171615141110987432128Feb252423221918171615141312111098732128Jan272017151413121110929Dec2322212017161514131110987632130Nov292625242319181716121198121Oct15141211987654129Sep242322212017161487632131Aug30292726252423201918171613121110986543229Jul2725232220191615141312987Fix wrong assignment of Xoff High crossed and CROSSED_LATCHED bits. They were reserved (see FLXUSERS-508)removed aurora bit assignement in LaneRegisterRemapper.vhdReplaced 4b_lcb with 4b_lcb_locked in ILAIncluded XOFF mechanism as described in FLX-1827:Added monitoring of WupperFifos full/empty/prog_full/prog_empty flags in BAR0 registersAdded SigasiProjectCreator submodule, Processed warnings from SigasiFixed assignment of ELINK_REALIGNMENT_STATUS for LTDB mode where we have > 12 channels per CR (but no 8b10b to monitor)added missing fikes to felig fileset and fixed FELIG specific genericsThe generic for switching on/off support of 32b elink width is added.Disable XOFF transmission mechanism in GBT mode 8b10b E-Links, enable in FULL modeInclude XOFF_FM_SOFT_XOFF register in the XOFF statistics measurementphase1 is not using a 32b chunk trailerFixed sigasi warningMerge remote-tracking branch 'origin/FLX-1834_Deadlock_debug_for_merge' into FLX-1827_ImprovedXOFF_masterMerge remote-tracking branch 'origin/FLX-1834_Deadlock_debug_for_merge' into FLX-1827_ImprovedXOFF_masterRegenerated dma_control, after removal of registerFLX-1834_Deadlo…FLX-1834_Deadlock_debug_for_mergeRemoved ILAs and GBT link crossing + necessary registers in FLX-1834, but kept some bugfixes that were done in the process, for a merge to masterBefore XOFF could be connected properly, I first needed to do some renaming and cleanup:connected RXUSRCLK for flx-info freq and reworked gc_multichannel_frequency_meter to fix timing violationsStrip decoders replace with DecEgroup_8b10b, according to FLX-1840.Tweaking column widthschanged filesets to reflect folder renamingremaned feligHG710 forder to FELIGchanged folder namecommented out ilasMerge branch 'FLX-1631_configurable-regmap-multi' of ssh://gitlab.cern.ch:7999/atlas-tdaq-felix/firmware into FLX-1631_configurable-regmap-multiFLX-1631_config…FLX-1631_configurable-regmap-multiUpdating TeX table generation to include defaultsfixes after merge. gbtAdded periodic XOFF / XON transmission to EPROC_OUT2_ENC8b10bAdded SigasiProjectCreator as a submoduleforgot to zero fecerrors before check them again in the unlock state1) reverted to default c_requiredTrueHeader; 2) added check for FEC corrections to lpgbtframealigner SM; 3) RXOUTCLK routed for freq computation (partial)Reverted another change that was forgotten in previous commitFLX-1834_Deadlo…FLX-1834_Deadlock_debugBack to Vivado 2020.1 for CIInstantiate ILA only for first 4 channels to save some resourcesMerge branch 'thea/fm_halfrate_rx_linerate_fix' into 'phase2/master'dune/v1.2.0_rc1dune/v1.2.0_rc1Changed freerunning clock frequency in ip core back to 40 MHzChanged scripts to use Vivado 2021.2 and machine learning to close timing. With the added debug probes, timing is difficult to reachgtwizard_fullmode_cpll_48g_ku core FREERUN_FREQUENCY set back to 40Regenerated dma_control_N.vhd for all flavours