Skip to content
Snippets Groups Projects
Select Git revision
  • 64b66b
  • 64b66b_48ch
  • 64b66b_mergemaster
  • AMAC_in_debug
  • AddCounters
  • AddTTCIlas
  • DRAFT_ENDEAVOR
  • DUNE_SCF-pkg
  • DirectModeFix
  • DualDescriptor_Merge
  • DuneDualDescriptorHFemu
  • FEI4backport
  • FLX-1055_FULL_noisy_links
  • FLX-1087_Roundrobin_revisited
  • FLX-1592_felig_amac
  • FLX-1631_configurable-regmap-multi
  • FLX-1697_TTC_Emulator_LongB_OCR_support_2
  • FLX-1834_Deadlock_debug
  • FLX-1834_Deadlock_debug_for_merge
  • FLX-1834_ImproveCDC
  • v4.15
  • rm-5.3
  • rm-5.2
  • v5.1
  • v4.14
  • v5.0-rc2
  • v5.0
  • rm-5.1
  • v5.0-rc1
  • rm-4.14
  • v4.13
  • rm-4.13
  • v4.12
  • rm-4.12
  • v4.11
  • FirstWorkingBCMFirmware
  • dune/v1.1.2
  • dune/v1.1.1
  • rm-4.11
  • v4.10
40 results
You can move around the graph by using the arrow keys.
Created with Raphaël 2.2.01Jul30Jun292829282724232221201716151413109876530May272625242320181712111064329Apr262522212019151413121198787654131Mar3029252423222118171615141110987432128Feb252423221918171615141312111098732128Jan272017151413121110929Dec2322212017161514131110987632130Nov2926252423Merge branch 'phase2/feligFLX712_FLX-1453_GBT_24ch_timing_constrains' into 'phase2/master'Updated waveform to debug memory wrapperRemoved all ILAsregisters clean upSerialize OCR, testpulse and other BROADCAST bits through b-channel. Undo change in EPROC_OUT8.vhd (TTC-option 7 was modified for some reason)Merge remote-tracking branch 'origin/master' into FLX-1892_TTC_Emulator_DebugMerge remote-tracking branch 'origin/phase2/FLX-1769_AddGBTForVCU128' into phase2/FLX-1428_AddRegistersphase2/FLX-1428…phase2/FLX-1428_AddRegistersFixed typo in if generate statement for 32b gearbox in DecEgroup_8b10bMerge branch 'phase2/FLX-1942_EVEN_DMA_desc3' into 'phase2/master'Inverted reset, the new fifo is a normal fifo with an active high resetAccidentally activated TRIG_IN port on memory ilaForgot to add extra probe in b347322changes to laneregistermap. added ila for registers (still need to add .xci to repo and fileset), removed lmk sm ila from FELIG_LpGBT_Wrapper.vhd.Fixed deserialization of serial b-channel in TTC Emulator (was rising/falling edge, but the start bit is always 0, followed by fmt (0 for short, 1 for long). Also the period in which the long B-channel was allowed (BCR period) was incorrect, so long and short could overlapAdded option to exclude certain e-paths in DecEgroup_8b10b, even if 8b is selected (See details: FLX-1941).downgraded IP's back to 2020.1, we are using 2020.1 for masterRegenerated pdf for rm5Test pulse logic and output position modifiedAdded ILA in itks_mem_wrapper for HCC 0Updated 240 MHz ILA to have L0a signalChanged the register remapper for the new lpgbt registers. FLX-1428Merge branch 'FLX-1892_TTC_Emulator_Debug' of https://gitlab.cern.ch/atlas-tdaq-felix/firmware into FLX-1892_TTC_Emulator_DebugPut xci files in wrong location in 385ca8fMerge branch 'FLXUSERS-292_AddXVCIla' of ssh://gitlab.cern.ch:7999/atlas-tdaq-felix/firmware into FLXUSERS-292_AddXVCIlaFLXUSERS-292_Ad…FLXUSERS-292_AddXVCIlaRemoved some clock domain crossings, added some CDCMerge branch 'phase2/FLX-1428_AddRegisters' into phase2/FLX-1428_FELIG_LPGBTAdded EPROC_OUT8 to the ttc_emulator_tb with some additional signal assignments that normally happen in ttc_fmc_wrapper_xilinx (latching broadcast bits) and centralRouter (extended testpulse)Added some control and monitor signals to ttc_emulator_tb.vhdFixed a typo in the evencycle_dma bit for DMA_STATUS 3 (the bit from descriptor 2 was assigned)Forgot to add new ILA xci files in b8c3caeUpdated 40->240 MHz LCB signal transitionLast commit didn't workRegenerating ILA on lane 0Separated itksemu ILAs to 40 and 240 clock domainsAdded DDR4 pins to felix_top_FLX182.xdcRemoved most set_max_delay constraints, and added XPM_CDC in gbt wrapperFELIG LPGBT aligns FLX-1428Disabled itksemu ILA generationPCIe (Dual CPM 2x gen4x8) now builds and imports fine for the BNL182Update EncodingEpathGBT in EncodingEpath_tbphase2/FLX-1940…phase2/FLX-1940_LpGBT_EC_HDLC_Flag