Introduction of overlaps between jFEXs and jFEXFPGAs for L1Calo Bitwise Software Simulation
Introduction of overlaps between jFEXs. Introduction of overlaps between jFEX FPGAs.
Primary changes involve modifying array sizes and shifting indices when filling them.
This code will be updated again in the future when extending the bitwise offline software simulation for jFEX to look at eta > 2.5. The plan is to complete that step in the coming week(s).