This MR is used to add in the jFEX Bitwise simulation the pile-up parameters obtained by the trigger performance group.
With this it changes the
PileupAndNoise.cxx file structure to make it friendly when the COOL database is built.
Calibration/jFEX_MatchedMapping.2021Oct14.r12406.root are read in the
jDriver.cxx file to fill the pileup parameters.
Both files are under the path
- Now the jFEX Bitwise is applying by default the pileup subtraction and noise cuts either for Jet and MET paths. This means that jFEX will run like we expect for Run3
- For Run2 we need to turn off the pileup and change (manually) the noise values to 3000 MeV (only for LAr)
- Adding the SumET Eta boundary in the FPGA.cxx File