Bugfixing C-side symmetry in the jFEX TOBs
This MR is meant to solve a bug in the local FPGA eta and phi. The C-side should be mirrored. The picture below shows one hemisphere for the globalEta (integer, using the local TOB eta) and the eta as a floating value
TOBs affected with this MR:
- L1_jFexTauRoI
- L1_jFexSRJetRoI
- L1_jFexLRJetRoI
It is expected that this changes the trigger counts, since seeding is done with the globalEta coordinate.
Edited by Sergi Rodriguez Bosca