FPGATrackSim: use THistSvc to create output ROOT data file

The output header tool now explicitly uses THistSvc if the "HEADER" mode is specified. The Python configuration now sets this by default, and creates a single output ROOT file for both of the trees (from the data prep and logical hits algorithms) to be written to-- so now we only have a single TFile again, just with two trees instead of one. This should make creating test vectors easier.

From PyROOT it should be possible to read the two trees using "friend trees" with something like this:

import ROOT
f = ROOT.TFile("test.root")
dataprep = f.FPGATrackSimDataPrepTree
tree = f.FPGATrackSimLogicalEventTree
tree.AddFriend(dataprep)

Then the branches of both trees can be accessed from tree when looping over events. Perhaps this is the best way to update the test vector code.

Tagging @jahreda and @tbold for review, plus @acamplan and @sabidi for test vector creation changes.