Add EDGE3 generation
I would like to generate a hierarchical EDGE3 design from my memory map. For example, from this top level cheby file:
https://gitlab.cern.ch/bi/BCT/BCTDC-DIDT-SPS/-/raw/master/hdl/cheby/BI_BCT24SPS.cheby
I would like to generate the following EDGE CSV file exactly:
https://gitlab.cern.ch/bi/BCT/BCTDC-DIDT-SPS/-/raw/master/sw/driver/bi_bct24sps_hw_desc.csv
Some notes:
I think blocks/submaps in the top level of the cheby file should become top level EDGE block instances. For example, in the top level I have two submaps called "System" and "Application" which should become:
block_inst_name, block_def_name, res_def_name, offset, description
System, System, Registers, 0x0, System registers
Application, Application, Registers, 0x800000, Application registers
Question: what to do about registers/etc in the top level??
Otherwise blocks/submaps inside the top level blocks/submaps should become EDGE sub-blocks. For example inside by "Application" block file I have submaps "BisCtrl", "IntIntlk", etc which become:
block_def_name, type, name, offset, rwmode, dwidth, depth, mask, flags, description
...
Application, BisCtrl, BisCtrl, 0x20, , , , , , BIS controller registers
Application, IntIntlk, IntInt, 0x40, , , , , , Intensity interlock registers
...
There probably need to be some x-edge
extensions:
- To avoid splitting some registers into fields.
- ???