functionality request: generate vhdl port with array or record
I don't think it's possibly today, didn't find it in the x-hdl documentation, but would it be possible to instead of having a separate port in/out lines for each register, have two lines (one in, one out) for all registers which then would be an array or record in case we'd want to include write/read strobes? This would allow for denser component ports and thus increase readability. To access by the user, cheby generated VHDL constants can be used (which would then need to include the array or record type).
Is there more interest for this or am I the only one? Would there be time to work on this?