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##### Cheby favours a description of the memory map in a dedicated text file. Another possibility is to annotate HDL files and extract from those files the information required for automatic generation of register/FIFO/RAM, software access, documentation, etc. What are the merits and disadvantages of each solution?
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Using annotated HDL files as several drawbacks:
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Using annotated HDL files has several drawbacks:
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* you need to write HDL (or at least skeletons) before being able to generate the memory map. This means your development is HW driven, while Cheby is neutral, you can start either with HW or SW.
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* you need to write HDL (or at least skeletons) before being able to generate the memory map. This means your development is HW driven, while Cheby is neutral: you can start with either HW or SW.
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* you need to a simple parser for verilog and VHDL, which is not that simple. Cheby needs to have writers for verilog and VHDL, which is simpler.
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* you need to a simple parser for Verilog and VHDL, which is not that simple. Cheby needs to have writers for Verilog and VHDL, which is simpler.
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On the other hand, with Cheby you need to learn a new data structure (the Cheby file format) which is slightly more complex than annotations.
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##### Cheby seems to favour designing using traditional HDLs. Have you looked at alternatives such as [Migen and MiSoc](https://m-labs.hk/migen/), and if so, what are in your opinion the relative merits of each approach?
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* Migen is a 'new' HDL based on python, which is far from being universal. It isn't easy to convince other team to use a different HDL. |
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* Migen is a 'new' HDL based on Python, which is far from being universal. It isn't easy to convince other teams to use a different HDL. |
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