Project 'be-cem-edl/diot/FMC-nanoFIP/fmc-nanofip-pcb' was moved to 'be-cem-edl/diot/worldfip/fmc-nanofip/fmc-nanofip-pcb'. Please update any links and bookmarks that may still have the old path.
Open
Milestone
layout-v3.1
All issues for this milestone are closed. You may close this milestone now.
Unstarted Issues (open and unassigned)
0
Ongoing Issues (open and assigned)
0
Completed Issues (closed)
13
- R78 and J2 seem to overlap
- Using the DRB TPS7A49 variant (VSON package) might lead to better reliability
- FMC VREF_A_M2C should be not connected
- Bottom: power tracks could be wider (currently they are 0.2mm)
- TPS7A49 (IC2, IC3, IC6) layout could be improved
- L3: unconnected stub of VBUS polygon between two tracks
- change silkscreen license text to CERN OHL-W v2
- add more stitching vias to connect well different GND planes
- L6: P1V5 polygon is spread over the whole PCB area with very few connections (vias)
- missing _N suffix for JC_TRST (instead of over-line)
- Test points: change to through hole and add labels
- '5M' label is slightly off
- Test points: TP1,2,3,4 very close to the front panel; cannot be probed
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