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Unverified Commit 6c5b6194 authored by Alen Arias Vazquez's avatar Alen Arias Vazquez :sunglasses:
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Charm test: add heartbeat for nanoFIP

parent 9cf4ff55
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...@@ -72,7 +72,8 @@ reuse: ...@@ -72,7 +72,8 @@ reuse:
- 'top/nanofip.vhd' - 'top/nanofip.vhd'
- 'top/Manifest.py' - 'top/Manifest.py'
artifacts: artifacts:
name: 'FMC-NANOFIP-${CI_COMMIT_REF_NAME}' name: 'FMC-NANOFIP-${CI_COMMIT_REF_NAME}-${CI_COMMIT_SHORT_SHA}'
when: on_success
paths: paths:
- artifacts - artifacts
......
...@@ -587,7 +587,6 @@ set_io rstpon_i \ ...@@ -587,7 +587,6 @@ set_io rstpon_i \
-fixed yes \ -fixed yes \
-DIRECTION Input -DIRECTION Input
set_io jc_tck_o \ set_io jc_tck_o \
-pinname 42 \ -pinname 42 \
-fixed yes \ -fixed yes \
...@@ -614,6 +613,10 @@ set_io jc_trst_n_o \ ...@@ -614,6 +613,10 @@ set_io jc_trst_n_o \
-res_pull down \ -res_pull down \
-DIRECTION Output -DIRECTION Output
set_io user0 \
-pinname 19 \
-fixed yes \
-DIRECTION Output
#set_io fd_rxcdn_i \ #set_io fd_rxcdn_i \
......
...@@ -261,7 +261,9 @@ entity nanofip is ...@@ -261,7 +261,9 @@ entity nanofip is
jc_trst_n_o: out std_logic; --! Drives the JTAG Test Reset jc_trst_n_o: out std_logic; --! Drives the JTAG Test Reset
jc_tms_o : out std_logic; --! Drives the JTAG Test Mode Select of the target TAP jc_tms_o : out std_logic; --! Drives the JTAG Test Mode Select of the target TAP
jc_tdi_o : out std_logic; --! Drives the JTAG Test Data In of the target TAP jc_tdi_o : out std_logic; --! Drives the JTAG Test Data In of the target TAP
jc_tck_o : out std_logic --! Drives the JTAG Test Clock of the target TAP jc_tck_o : out std_logic; --! Drives the JTAG Test Clock of the target TAP
--! User pins
user0 : out std_logic
); );
end entity nanofip; end entity nanofip;
...@@ -321,6 +323,9 @@ architecture struc of nanofip is ...@@ -321,6 +323,9 @@ architecture struc of nanofip is
signal u_pacer : std_logic; signal u_pacer : std_logic;
signal u_cacer : std_logic; signal u_cacer : std_logic;
signal r_fcser : std_logic; signal r_fcser : std_logic;
--! Hearbeat counter
signal s_heartbeat_c : unsigned(24 downto 0);
signal s_heartbeat : std_logic;
--============================================================================== --==============================================================================
--! Architecture begin --! Architecture begin
...@@ -551,6 +556,28 @@ begin ...@@ -551,6 +556,28 @@ begin
jc_trst_n_o <= s_jc_trst; jc_trst_n_o <= s_jc_trst;
----------------------------------------------------------------------------
--! CHARM Test heartbeat
p_heartbeat: process(uclk_i)
begin
if rising_edge(uclk_i) then
if s_nfip_intern_rst = '1' then
s_heartbeat_c <= (others => '0');
s_heartbeat <= '0';
else
if s_heartbeat_c = x"1312CFF" then
s_heartbeat_c <= (others => '0');
s_heartbeat <= not(s_heartbeat);
else
s_heartbeat_c <= s_heartbeat_c + 1;
s_heartbeat <= s_heartbeat;
end if;
end if;
end if;
end process p_heartbeat;
user0 <= s_heartbeat;
end architecture struc; end architecture struc;
--============================================================================== --==============================================================================
--! Architecture end --! Architecture end
......
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