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Created with Raphaël 2.2.018Mar1711Nov710May87229Apr26821Mar15527Feb6Sep28Aug30May57Jan28May24Mar2028Feb18Jan15Dec18Nov171615141331Oct7Sep31Aug5Jul30Jun2413Apr24Mar22212123Feb181631Jan27262524211817125Nov425Oct27Sep222017161331Aug27265322Apr1514129826Mar171117Feb819Oct1615624Sep10Jul610FebCharm test: add heartbeat for nanoFIPuse-port-user0-…use-port-user0-debugCharm test: add heartbeat for nanoFIPMerge branch 'clean-top-level-add-licenses' into 'master'mastermasterMerge branch 'check-ci4fpga' into 'master'add licensing to the project and clean the top leveltry ci4fpga with libero 11.9Merge branch 'bring-evergreen' into 'master'update CI/CD to the BE/CEM/EDL procedureexploring JTAG programming alternativestest-alternativ…test-alternative-jtagMerge branch '4-trst-is-not-driven' into 'master'Merge branch 'kostas_jtag_rtsb' into '4-trst-is-not-driven'add src to the CI build scriptMerge remote-tracking branch 'origin/master' into kostas_jtag_rtsbMerge branch 'increase-time-reset-output-to-carrier' into 'master'Rename signals that control the (de)assertion of the RSTON signal to be independent of the value. Define new constants to refer the WIDTH and the values of the counter that controls RSTON state.Merge remote-tracking branch 'origin/master' into increase-time-reset-output-to-carrierMerge branch '1-add-ci-cd' into 'master'commit to test CI/CD for docsrestore Manifest files for HDLMakecheck hostname- adding more debug to build scriptadded extended job to build gwadded before script: modify path to find liberoarrange documentationadded CI/CDremove unused files in the buildclean tabs from TCL scriptMerge branch '2-build-tcl' into 'master'remove duplicity in contraints and added script for build the gateware. Add documentation to evergreen styleedited reset timer from nanofip with a counter of 32bMerge branch 'eva_fmc_nanoFIP_v3' into 'master'remove duplicity in contraints and added script for build the gatewareREADME added with some instruction on how to build and flash NanofipJTAG TRST controller introduced. It allows to reprogram the Rad-Tol DI/OT SB through worldfipAdd outputs for testpointstestpoints-errtestpoints-errKeep p3 length constant and independent of the board pins for profip testingprofip_testprofip_testGW: single nanofip device can be multiple agents (3 to 125)HDL: jtag pins are now in 'Z' when IDLE. Pull down specified for TDI, TMS in constraint. FIX in the TCL for building the projectSet the JTAG pins in the top level design to be 'Z' so as to program the RT-SB without unpluging the fmc-nanonip. Tested in V2 SB but needs to be done in a more elegant wayRemove the define_clock from Synplufy_Constraint.sdc since it is declared also in the other sdc file. Added build_nanofip.tcl script to automate the build of the project