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Commit 91d145bc authored by Christos Gentsos's avatar Christos Gentsos
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Connect FPGA I/O bank decoupling capacitors to Vadj (closes #25)

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......@@ -580,50 +580,50 @@ $EndComp
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......@@ -921,17 +921,6 @@ F 41 "Capacitors SMD" H 0 0 60 0001 C CNN "Footprint Library"
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......@@ -1081,50 +1070,50 @@ $EndComp
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......@@ -2952,4 +2941,15 @@ Connection ~ 9000 3100
Connection ~ 9000 3000
Wire Wire Line
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