Add the Design Office's layout work

EDA-03613-V3-1-rescue.dcm

+EESchema-DOCLIB  Version 2.0
+#
+#End Doc Library

EDA-03613-V3-1.drl

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EDA-03613-V3-1.pro

-update=15/05/2018 16:36:11
+update=03-Dec-21 13:04:54
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+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
+Enabled=1
+[pcbnew/Layer.F.Mask]
+Enabled=1
+[pcbnew/Layer.Dwgs.User]
+Enabled=1
+[pcbnew/Layer.Cmts.User]
+Enabled=1
+[pcbnew/Layer.Eco1.User]
+Enabled=1
+[pcbnew/Layer.Eco2.User]
+Enabled=1
+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
+Enabled=1
+[pcbnew/Layer.F.CrtYd]
+Enabled=1
+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=0
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.2
+TrackWidth=0.25
+ViaDiameter=0.6
+ViaDrill=0.3
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[pcbnew/Netclasses/1]
+Name=PairDiff
+Clearance=0.4
+TrackWidth=0.2
+ViaDiameter=0.6
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.4
+dPairViaGap=0.25

sym-lib-table

-(sym_lib_table
-  (lib (name EDA-03613)(type Legacy)(uri "$(KIPRJMOD)/EDA-03613.lib")(options "")(descr ""))
-)
+(sym_lib_table
+  (lib (name EDA-03613)(type Legacy)(uri "$(KIPRJMOD)/EDA-03613.lib")(options "")(descr ""))
+  (lib (name EDA-03613-V3-1-rescue)(type Legacy)(uri ${KIPRJMOD}/EDA-03613-V3-1-rescue.lib)(options "")(descr ""))
+)