generic_dpram_mod.v not useable for address width > 12 bits
Trying to synthesise generic_dpram_mod.v in Quartus with an address width > 12 bits gives the following error:
Error (10106): Verilog HDL Loop error at generic_dpram_mod.v(157): loop must terminate within 5000 iterations
This comes from the initialisation code loop:
integer i; //MBM
initial begin //MBM
for (i=0;i<(2**aw);i=i+1) mem[i] = {dw{1'b0}}; //MBM
end