Turn clock delay?
The current implementation of the turn clock delay does not make sense to me. The value of the TurnClkFlagDly_ib12
corresponds to a delay in 160 MHz clocks. However, 12 bits is not enough for a complete turn of the LHC. With 3564 x 4 clock periods we would need 14 bits of delay. Also, why is this an input from the application and not a VME register?
In addition for correct reception of the BST message we would need the un-delayed turn clock to latch the message. Using a the delayed version would result in the possibility of latching a corrupt message.
I would propose the following...
- Remove the existing
TurnClkFlagDly_ib12
from the Application to the System. - Add a new VME register inside the BST decoder core to implement the delay.
- Provide a new
BunchClkFlagDelayed_i
andTurnClkFlagDelayed_i
to the Application. - Provide a module to delay the turn clock which can be used in the Application.
This allows for the simple case where someone wants a single set of delayed bunch and turn clocks controlled via VME. If someone wants to implement something more complicated in the Application they then can.