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bi
HDL_Cores
VFC_DDR3
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ddr_iam_570MHz
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4
quartus_20.1.1_hdlmake
master
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ddr_iam_570MHz
quartus_19.1_600MHz_clock
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quartus_19.1
quartus_17.1
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VFC_DDR3
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ssh://git@gitlab.cern.ch:7999/bi/HDL_Cores/VFC_DDR3.git
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https://gitlab.cern.ch/bi/HDL_Cores/VFC_DDR3.git
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reverting back to 533/125MHz
David Belohrad
authored
4 years ago
9e01162e
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9e01162e
4 years ago
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Ddr3M
Ddr3S
doc
sim
TopVfcDdr3.sv
VfcDdr3.qip
VfcDdr3.sip
VfcDdr3.sv
VfcDdr3Interface.sv
VfcDdr3Interface_WSVI.sv
VfcDdr3WbToAvl.sv
VfcDdr3WbToAvlWithFetch.sv
VfcDdr3_WSVI.sv
generate_ip_cores.cmd
