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Commit 87da12d6 authored by Andrew Peck's avatar Andrew Peck
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add FIFOs between each etroc and the main daq mux

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README.md
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......@@ -34,6 +34,11 @@ only use the versions listed here unless instructed otherwise.
- Deprecate software fast commands
- ILA additions, disable wishbone ILA by default
- Add enable signal for external SMA trigger
- FIFO reset will be 8 clocks long automatically, no need to double
clock in software
- Added a compile-time mask to disable unconnected elinks
- Added shallow FIFOs at the output of each ETROC decoder which feed
into the main DAQ FIFO, in preparation for an event merger
### v1.4.0
......
README.org
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− 0
View file @ 87da12d6
......@@ -34,6 +34,9 @@ Change log is inclusive of all changes from the previous recommended version; pl
- Deprecate software fast commands
- ILA additions, disable wishbone ILA by default
- Add enable signal for external SMA trigger
- FIFO reset will be 8 clocks long automatically, no need to double clock in software
- Added a compile-time mask to disable unconnected elinks
- Added shallow FIFOs at the output of each ETROC decoder which feed into the main DAQ FIFO, in preparation for an event merger
*** v1.4.0
- Fix bitslip / zero_suppress / raw_data_mode bitmask connection (previously
bit0 was connected to all 28 elinks, now it will be a bitmask)
......
src/readout_board/readout_board.vhd
+ 127
− 62
View file @ 87da12d6
......@@ -60,6 +60,11 @@ end readout_board;
architecture behavioral of readout_board is
signal fifo_reset : std_logic := '0';
signal fifo_reset_cnt : integer range 0 to 7 := 0;
constant ELINK_EN_MASK : std_logic_vector (27 downto 0) := x"0055555";
constant NUM_UPLINKS : integer := NUM_LPGBTS_DAQ + NUM_LPGBTS_TRIG;
constant FREQ : integer := 320; -- uplink frequency
......@@ -144,7 +149,6 @@ architecture behavioral of readout_board is
signal l1a_gen : std_logic := '0';
signal l1a : std_logic := '0';
signal bc0 : std_logic := '0';
signal link_reset : std_logic := '0';
signal bxn : natural range 0 to 3563 := 0;
--------------------------------------------------------------------------------
......@@ -180,6 +184,26 @@ architecture behavioral of readout_board is
begin
process (clk40) is
begin
if (rising_edge(clk40)) then
if (ctrl.fifo_reset = '1') then
fifo_reset_cnt <= 7;
elsif (fifo_reset_cnt > 0) then
fifo_reset_cnt <= fifo_reset_cnt - 1;
end if;
if (fifo_reset_cnt = 0) then
fifo_reset <= '0';
else
fifo_reset <= '1';
end if;
end if;
end process;
--------------------------------------------------------------------------------
-- create 1/8 strobe synced to 40MHz clock
......@@ -286,7 +310,7 @@ begin
reset => reset,
l1a => l1a,
bc0 => bc0,
link_reset => link_reset,
link_reset => ctrl.link_reset_pulse,
data_o => fast_cmd_fw
);
......@@ -299,14 +323,15 @@ begin
trig => l1a_gen
);
process (clk40) is
begin
if (rising_edge(clk40)) then
l1a <= ctrl.l1a_pulse or l1a_gen or (trigger_i and ctrl.en_ext_trigger);
trigger_o <= l1a;
end if;
end process;
bc0 <= '1' when bxn = 0 else '0';
l1a <= ctrl.l1a_pulse or l1a_gen or (trigger_i and ctrl.en_ext_trigger);
link_reset <= ctrl.link_reset_pulse;
trigger_o <= l1a;
process (clk40) is
begin
if (rising_edge(clk40)) then
......@@ -643,64 +668,104 @@ begin
etroc_rx_lpgbt_gen : for ilpgbt in 0 to NUM_UPLINKS-1 generate
etroc_rx_elink_gen : for ielink in 0 to 27 generate
signal locked : std_logic := '0';
signal bitslip : std_logic := '0';
signal zero_suppress : std_logic := '1';
signal raw_data_mode : std_logic := '0';
signal data_i : std_logic_vector (31 downto 0);
begin
en_gen : if (ELINK_EN_MASK(ielink) = '1') generate
data_i <= x"000000" & uplink_data_aligned(ilpgbt).data(8*(ielink+1)-1 downto 8*ielink);
signal data_i : std_logic_vector (31 downto 0);
signal data : std_logic_vector (39 downto 0) := (others => '0');
etroc_rx_1 : entity etroc.etroc_rx
port map (
clock => clk40,
-- FIXME: this should not be shared across both lpgbts
reset => reset or ctrl.reset_etroc_rx(ielink),
data_i => data_i,
bitslip_i => bitslip,
bitslip_auto_i => ctrl.bitslip_auto_en,
zero_suppress => zero_suppress,
raw_data_mode => raw_data_mode,
fifo_wr_en_o => rx_fifo_wr_en_arr(ilpgbt*28+ielink),
fifo_data_o => rx_fifo_data_arr(ilpgbt*28+ielink),
frame_mon_o => rx_frame_mon_arr(ilpgbt*28+ielink),
state_mon_o => rx_state_mon_arr(ilpgbt*28+ielink),
bcid_o => open,
type_o => open,
event_cnt_o => open,
cal_o => open,
tot_o => open,
toa_o => open,
col_o => open,
row_o => open,
ea_o => open,
data_en_o => open,
stat_o => open,
hitcnt_o => open,
crc_o => rx_crc_arr(ilpgbt*28+ielink),
crc_calc_o => rx_crc_calc_arr(ilpgbt*28+ielink),
chip_id_o => open,
start_of_packet_o => rx_start_of_packet(ilpgbt*28+ielink),
end_of_packet_o => rx_end_of_packet(ilpgbt*28+ielink),
err_o => rx_err(ilpgbt*28+ielink),
busy_o => rx_busy(ilpgbt*28+ielink),
idle_o => rx_idle(ilpgbt*28+ielink),
locked_o => rx_locked(ilpgbt*28+ielink)
);
signal locked : std_logic := '0';
signal bitslip : std_logic := '0';
signal zero_suppress : std_logic := '1';
signal raw_data_mode : std_logic := '0';
signal start_of_packet : std_logic := '0';
signal end_of_packet : std_logic := '0';
signal wr_en : std_logic := '0';
signal rd_en : std_logic := '0';
lpgbt0 : if (ilpgbt = 0) generate
bitslip <= ctrl.etroc_bitslip(ielink);
zero_suppress <= ctrl.zero_supress(ielink);
raw_data_mode <= ctrl.raw_data_mode(ielink);
end generate;
begin
lpgbt1 : if (ilpgbt = 1) generate
bitslip <= ctrl.etroc_bitslip_slave(ielink);
zero_suppress <= ctrl.zero_supress_slave(ielink);
raw_data_mode <= ctrl.raw_data_mode_slave(ielink);
end generate;
data_i <= x"000000" & uplink_data_aligned(ilpgbt).data(8*(ielink+1)-1 downto 8*ielink);
etroc_rx_1 : entity etroc.etroc_rx
port map (
clock => clk40,
-- FIXME: this should not be shared across both lpgbts
reset => reset or ctrl.reset_etroc_rx(ielink),
data_i => data_i,
bitslip_i => bitslip,
bitslip_auto_i => ctrl.bitslip_auto_en,
zero_suppress => zero_suppress,
raw_data_mode => raw_data_mode,
fifo_wr_en_o => wr_en,
fifo_data_o => data,
frame_mon_o => rx_frame_mon_arr(ilpgbt*28+ielink),
state_mon_o => rx_state_mon_arr(ilpgbt*28+ielink),
bcid_o => open,
type_o => open,
event_cnt_o => open,
cal_o => open,
tot_o => open,
toa_o => open,
col_o => open,
row_o => open,
ea_o => open,
data_en_o => open,
stat_o => open,
hitcnt_o => open,
crc_o => rx_crc_arr(ilpgbt*28+ielink),
crc_calc_o => rx_crc_calc_arr(ilpgbt*28+ielink),
chip_id_o => open,
start_of_packet_o => start_of_packet,
end_of_packet_o => end_of_packet,
err_o => rx_err(ilpgbt*28+ielink),
busy_o => rx_busy(ilpgbt*28+ielink),
idle_o => rx_idle(ilpgbt*28+ielink),
locked_o => locked
);
rx_locked(ilpgbt*28+ielink) <= locked;
rd_en <= '1' when ilpgbt*28+ielink = link_sel else '0';
-- buffer data from THIS etroc before it goes into the main mux
etroc_fifo_inst : entity work.fifo_async
generic map (
DEPTH => 512,
WR_WIDTH => 42,
RD_WIDTH => 42,
RELATED_CLOCKS => 1
)
port map (
rst => reset or fifo_reset, -- Must be synchronous to wr_clk. Must be applied only when wr_clk is stable and free-running.
wr_clk => clk40,
rd_clk => clk40,
wr_en => wr_en,
rd_en => rd_en,
din => start_of_packet & end_of_packet & data,
dout(39 downto 0) => rx_fifo_data_arr(ilpgbt*28+ielink),
dout(40) => rx_end_of_packet(ilpgbt*28+ielink),
dout(41) => rx_start_of_packet(ilpgbt*28+ielink),
valid => rx_fifo_wr_en_arr(ilpgbt*28+ielink),
full => open,
empty => open
);
lpgbt0 : if (ilpgbt = 0) generate
bitslip <= ctrl.etroc_bitslip(ielink);
zero_suppress <= ctrl.zero_supress(ielink);
raw_data_mode <= ctrl.raw_data_mode(ielink);
end generate;
lpgbt1 : if (ilpgbt = 1) generate
bitslip <= ctrl.etroc_bitslip_slave(ielink);
zero_suppress <= ctrl.zero_supress_slave(ielink);
raw_data_mode <= ctrl.raw_data_mode_slave(ielink);
end generate;
end generate;
end generate;
end generate;
......@@ -743,7 +808,7 @@ begin
port map (
clk40 => clk40,
reset => reset,
fifo_reset_i => ctrl.fifo_reset,
fifo_reset_i => fifo_reset,
lost_word_cnt => mon.rx_fifo_lost_word_cnt,
full_o => mon.rx_fifo_full,
fifo_data_i => rx_fifo_data_mux,
......
src/utils/fifo_async.vhd
+ 4
− 3
View file @ 87da12d6
......@@ -9,7 +9,8 @@ entity fifo_async is
DEPTH : integer := 16;
WR_WIDTH : integer := 16;
RD_WIDTH : integer := 16;
FIFO_READ_LATENCY : integer := 1
FIFO_READ_LATENCY : integer := 1;
RELATED_CLOCKS : integer := 0
);
port (
rst : in std_logic;
......@@ -46,7 +47,7 @@ begin
xpm_fifo_async_inst : xpm_fifo_async
generic map (
CDC_SYNC_STAGES => 4, -- DECIMAL
CDC_SYNC_STAGES => 2, -- DECIMAL
DOUT_RESET_VALUE => "0", -- String
ECC_MODE => "no_ecc", -- no_ecc, en_ecc
FIFO_MEMORY_TYPE => "auto", -- auto, block, distributed, ultra
......@@ -58,7 +59,7 @@ begin
RD_DATA_COUNT_WIDTH => 5, -- DECIMAL
READ_DATA_WIDTH => RD_WIDTH, -- DECIMAL
read_mode => "std", -- std or fwft
RELATED_CLOCKS => 0, -- DECIMAL
RELATED_CLOCKS => RELATED_CLOCKS, -- DECIMAL
USE_ADV_FEATURES => USE_ADV_FEATURES_STR, -- String
WAKEUP_TIME => 0, -- 0 = disable sleep, 2 = use sleep pin
WRITE_DATA_WIDTH => WR_WIDTH, -- DECIMAL
......
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