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Commit aa33a3a8 authored by Andrew Peck's avatar Andrew Peck
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connect global qinj to etrocs

parent e7a23415
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1 merge request!63Switchable FEC mode
......@@ -179,7 +179,7 @@ architecture behavioral of etl_test_fw is
-- TTC
--------------------------------------------------------------------------------
signal bc0, l1a : std_logic;
signal bc0, l1a, qinj : std_logic;
signal ext_trigger : std_logic;
signal trigger_o : std_logic_vector (NUM_RBS-1 downto 0);
signal l1a_rate_cnt : std_logic_vector (31 downto 0);
......@@ -612,6 +612,7 @@ begin
reset => reset,
l1a => l1a,
bc0 => bc0,
qinj => qinj,
force_trig => system_ctrl.l1a_pulse,
ext_trig => ext_trigger,
ext_trig_en => system_ctrl.en_ext_trigger,
......@@ -660,8 +661,9 @@ begin
reset => reset,
-- ttc
bc0 => bc0,
l1a => l1a,
bc0 => bc0,
l1a => l1a,
qinj => qinj,
-- DAQ wishbone
daq_wb_in => daq_ipb_w_array(I downto I),
......
......@@ -39,8 +39,9 @@ entity readout_board is
strobe : in std_logic;
bc0 : in std_logic;
l1a : in std_logic;
bc0 : in std_logic;
qinj : in std_logic;
l1a : in std_logic;
mon : out READOUT_BOARD_MON_t;
ctrl : in READOUT_BOARD_CTRL_t;
......@@ -283,9 +284,9 @@ begin
reset => reset,
l1a_i => l1a or ctrl.l1a_pulse,
bc0 => bc0 or ctrl.bc0_pulse,
qinj => qinj or ctrl.qinj_pulse,
ecr => ctrl.ecr_pulse,
link_reset => ctrl.link_reset_pulse,
qinj => ctrl.qinj_pulse,
l1a_qinj => ctrl.l1a_qinj_pulse,
l1a_inj_dly => ctrl.l1a_inj_dly,
ws_stop => ctrl.ws_stop_pulse,
......
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