Fixed logic errors on flash_bit

src/readout_board/flash_bit.vhd

@@ -6,19 +6,19 @@ use ieee.math_real.all;
 
 entity flash_bit is
   generic
-  (
-    g_DATA_WIDTH : integer := 8
-  );
+    (
+      g_DATA_WIDTH : integer := 8
+      );
   port
-  (
-    clk_i   : in std_logic;
-    reset_i : in std_logic;
-    data_i  : in std_logic_vector(g_DATA_WIDTH - 1 downto 0);
+    (
+      clk_i   : in std_logic;
+      reset_i : in std_logic;
+      data_i  : in std_logic_vector(g_DATA_WIDTH - 1 downto 0);
 
-    data_o   : out std_logic_vector(g_DATA_WIDTH - 1 downto 0);
-    active_o : out std_logic
+      data_o   : out std_logic_vector(g_DATA_WIDTH - 1 downto 0);
+      active_o : out std_logic
 
-  );
+      );
 end flash_bit;
 
 architecture behavioral of flash_bit is
@@ -27,7 +27,6 @@ architecture behavioral of flash_bit is
   signal cnt_clk                  : std_logic_vector(13 downto 0);
   signal start                    : std_logic;
   signal active                   : std_logic;
-  constant all_ones               : std_logic_vector(g_DATA_WIDTH - 1 downto 0) := (others => '1');
   attribute MARK_DEBUG            : string;
   attribute MARK_DEBUG of cnt     : signal is "true";
   attribute MARK_DEBUG of cnt_clk : signal is "true";
@@ -38,69 +37,78 @@ begin
 
   process (clk_i) is
   begin
-    if rising_edge(clk_i) and reset_i = '1' then
-      --------------------------------------------------------------------------------
-      -- Reset
-      --------------------------------------------------------------------------------
-      active  <= '0';
-      start   <= '0';
-      cnt     <= (others => '0');
-      cnt_clk <= (others => '0');
-      data_o  <= data_i;
-    else
-
-      --------------------------------------------------------------------------------
-      -- Start Count
-      --------------------------------------------------------------------------------
-      if data_i = all_ones and start = '0' then
-        start   <= '1';
-        cnt_clk <= std_logic_vector(unsigned(cnt_clk) + 1);
-        cnt     <= std_logic_vector(unsigned(cnt) + 1);
-      end if;
+    if rising_edge(clk_i) then
 
-      --------------------------------------------------------------------------------
-      -- Increase Clock Count
-      --------------------------------------------------------------------------------
-      if start = '1' then
-        case to_integer(unsigned(cnt_clk)) is
-          when 0 to 3643 =>
-            cnt_clk <= std_logic_vector(unsigned(cnt_clk) + 1);
-            data_o  <= data_i;
-          when others        =>
-            cnt_clk <= (others => '0');
-        end case;
-      end if;
+      if (reset_i = '1') then
+        --------------------------------------------------------------------------------
+        -- Reset
+        --------------------------------------------------------------------------------
+        active  <= '0';
+        start   <= '0';
+        cnt     <= (others => '0');
+        cnt_clk <= (others => '0');
+        data_o  <= data_i;
+
+      else
+
+        --------------------------------------------------------------------------------
+        -- Start Count
+        --------------------------------------------------------------------------------
+
+        if (and_reduce(data_i) = '1' and start = '0') then
+          start   <= '1';
+          cnt_clk <= std_logic_vector(unsigned(cnt_clk) + 1);
+          cnt     <= std_logic_vector(unsigned(cnt) + 1);
+        end if;
+
+        --------------------------------------------------------------------------------
+        -- Increase Clock Count
+        --------------------------------------------------------------------------------
+
+        if start = '1' then
+          case to_integer(unsigned(cnt_clk)) is
+            when 0 to 3643 =>
+              cnt_clk <= std_logic_vector(unsigned(cnt_clk) + 1);
+              data_o  <= data_i;
+            when others =>
+              cnt_clk <= (others => '0');
+          end case;
+        end if;
+
+        --------------------------------------------------------------------------------
+        -- Check Flashing Bit seen
+        --------------------------------------------------------------------------------
 
-      --------------------------------------------------------------------------------
-      -- Check Flashing Bit seen
-      --------------------------------------------------------------------------------
-      if to_integer(unsigned(cnt_clk)) = 3644 then
-        case data_i is
-          when all_ones =>
-            cnt <= std_logic_vector(unsigned(cnt) + 1);
-          when others      =>
+        if to_integer(unsigned(cnt_clk)) = 3644 then
+
+          if (and_reduce(data_i) = '1') then
+            cnt   <= std_logic_vector(unsigned(cnt) + 1);
+            start <= start;
+          else
             cnt   <= (others => '0');
             start <= '0';
-        end case;
-      end if;
+          end if;
 
-      --------------------------------------------------------------------------------
-      -- Activate if flashing bit is on 5 clock cycle times in a row
-      --------------------------------------------------------------------------------
-      if (rising_edge(clk_i) and to_integer(unsigned(cnt)) >= 5) then
-        active <= '1';
-        cnt    <= std_logic_vector(to_unsigned(5, cnt'length));
-      end if;
+        end if;
+
+        --------------------------------------------------------------------------------
+        -- Activate if flashing bit is on 5 clock cycle times in a row
+        --------------------------------------------------------------------------------
+
+        if (to_integer(unsigned(cnt)) >= 5) then
+          active <= '1';
+          cnt    <= std_logic_vector(to_unsigned(5, cnt'length));
+        end if;
+
+        --------------------------------------------------------------------------------
+        -- Clear if flashing bit is active and correct clock cycle
+        --------------------------------------------------------------------------------
 
-      --------------------------------------------------------------------------------
-      -- Clear if flashing bit is active and correct clock cycle
-      --------------------------------------------------------------------------------
-      if (rising_edge(clk_i)) then
         if active = '1' and to_integer(unsigned(cnt_clk)) = 3644 then
           data_o <= (others => '0');
         end if;
-      end if;
 
+      end if;
     end if;
   end process;
 end behavioral;
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