Made fec_mode an array for each individual uplink

registers/READOUT_BOARD_PKG.vhd

@@ -13,11 +13,13 @@ package READOUT_BOARD_CTRL is
 
   type READOUT_BOARD_LPGBT_UPLINK_CTRL_t is record
     RESET                      :std_logic;     -- Reset this Uplink
+    FEC_MODE                   :std_logic;     -- 1 = FEC12 | 0 = FEC5
   end record READOUT_BOARD_LPGBT_UPLINK_CTRL_t;
   type READOUT_BOARD_LPGBT_UPLINK_CTRL_t_ARRAY is array(0 to 1) of READOUT_BOARD_LPGBT_UPLINK_CTRL_t;
 
   constant DEFAULT_READOUT_BOARD_LPGBT_UPLINK_CTRL_t : READOUT_BOARD_LPGBT_UPLINK_CTRL_t := (
-                                                                                             RESET => '0'
+                                                                                             RESET => '0',
+                                                                                             FEC_MODE => '1'
                                                                                             );
   type READOUT_BOARD_LPGBT_DOWNLINK_MON_t is record
     READY                      :std_logic;     -- LPGBT Downlink Ready

registers/READOUT_BOARD_map.vhd

@@ -62,9 +62,11 @@ begin  -- architecture behavioral
         case to_integer(unsigned(wb_addr(10 downto 0))) is
           when 1 => --0x1
           localRdData( 0)            <=  Mon.LPGBT.UPLINK(0).READY;                   --LPGBT Uplink Ready
+          localRdData( 1)            <=  reg_data( 1)( 1);                            --1 = FEC12 | 0 = FEC5
           localRdData(31 downto 16)  <=  Mon.LPGBT.UPLINK(0).FEC_ERR_CNT;             --Data Corrected Count
         when 17 => --0x11
           localRdData( 0)            <=  Mon.LPGBT.UPLINK(1).READY;                   --LPGBT Uplink Ready
+          localRdData( 1)            <=  reg_data(17)( 1);                            --1 = FEC12 | 0 = FEC5
           localRdData(31 downto 16)  <=  Mon.LPGBT.UPLINK(1).FEC_ERR_CNT;             --Data Corrected Count
         when 33 => --0x21
           localRdData( 0)            <=  Mon.LPGBT.DOWNLINK.READY;                    --LPGBT Downlink Ready
@@ -184,6 +186,8 @@ begin  -- architecture behavioral
 
 
   -- Register mapping to ctrl structures
+  Ctrl.LPGBT.UPLINK(0).FEC_MODE                <=  reg_data( 1)( 1);                 
+  Ctrl.LPGBT.UPLINK(1).FEC_MODE                <=  reg_data(17)( 1);                 
   Ctrl.LPGBT.DOWNLINK.DL_SRC                   <=  reg_data(35)( 3 downto  0);       
   Ctrl.LPGBT.PATTERN_CHECKER.CHECK_PRBS_EN_0   <=  reg_data(67)(31 downto  0);       
   Ctrl.LPGBT.PATTERN_CHECKER.CHECK_UPCNT_EN_0  <=  reg_data(68)(31 downto  0);       
@@ -265,8 +269,12 @@ begin  -- architecture behavioral
         case to_integer(unsigned(wb_addr(10 downto 0))) is
         when 0 => --0x0
           Ctrl.LPGBT.UPLINK(0).RESET            <=  localWrData( 0);               
+        when 1 => --0x1
+          reg_data( 1)( 1)                      <=  localWrData( 1);                --1 = FEC12 | 0 = FEC5
         when 16 => --0x10
           Ctrl.LPGBT.UPLINK(1).RESET            <=  localWrData( 0);               
+        when 17 => --0x11
+          reg_data(17)( 1)                      <=  localWrData( 1);                --1 = FEC12 | 0 = FEC5
         when 31 => --0x1f
           Ctrl.LPGBT.FEC_ERR_RESET              <=  localWrData( 6);               
         when 32 => --0x20
@@ -388,7 +396,9 @@ begin  -- architecture behavioral
       -- synchronous reset (active high)
       if reset = '1' then
       reg_data( 0)( 0)  <= DEFAULT_READOUT_BOARD_CTRL_t.LPGBT.UPLINK(0).RESET;
+      reg_data( 1)( 1)  <= DEFAULT_READOUT_BOARD_CTRL_t.LPGBT.UPLINK(0).FEC_MODE;
       reg_data(16)( 0)  <= DEFAULT_READOUT_BOARD_CTRL_t.LPGBT.UPLINK(1).RESET;
+      reg_data(17)( 1)  <= DEFAULT_READOUT_BOARD_CTRL_t.LPGBT.UPLINK(1).FEC_MODE;
       reg_data(31)( 6)  <= DEFAULT_READOUT_BOARD_CTRL_t.LPGBT.FEC_ERR_RESET;
       reg_data(32)( 0)  <= DEFAULT_READOUT_BOARD_CTRL_t.LPGBT.DOWNLINK.RESET;
       reg_data(35)( 3 downto  0)  <= DEFAULT_READOUT_BOARD_CTRL_t.LPGBT.DOWNLINK.DL_SRC;

registers/ipbus_decode_etl_test_fw.vhd

@@ -17,7 +17,7 @@ package ipbus_decode_etl_test_fw is
   subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
   function ipbus_sel_etl_test_fw(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
 
--- START automatically generated VHDL (Tue May 23 18:36:42 2023)
+-- START automatically generated VHDL (Wed Jul 19 14:20:59 2023)
   constant N_SLV_LOOPBACK: integer := 0;
   constant N_SLV_FW_INFO: integer := 1;
   constant N_SLV_READOUT_BOARD_0: integer := 2;
@@ -43,7 +43,7 @@ package body ipbus_decode_etl_test_fw is
     variable sel: ipbus_sel_t;
   begin
 
--- START automatically generated VHDL (Tue May 23 18:36:42 2023)
+-- START automatically generated VHDL (Wed Jul 19 14:20:59 2023)
     if    std_match(addr, "-------00000----0000------------") then
       sel := ipbus_sel_t(to_unsigned(N_SLV_LOOPBACK, IPBUS_SEL_WIDTH)); -- LOOPBACK / base 0x00000000 / mask 0x01f0f000
     elsif std_match(addr, "-------00000----0001------------") then

src/readout_board/readout_board.vhd

@@ -435,7 +435,8 @@ begin
       downlink_clk => clk320,
       uplink_clk   => clk320,
 
-      fec_mode_i => '0',
+      fec_mode_i(0) => ctrl.lpgbt.uplink(0).fec_mode,
+      fec_mode_i(1) => ctrl.lpgbt.uplink(1).fec_mode,
 
       downlink_reset_i(0) => ctrl.lpgbt.downlink.reset,
 

src/wrappers/lpgbt_link_wrapper.vhd

@@ -87,7 +87,7 @@ entity lpgbt_link_wrapper is
     uplink_ready_o : out std_logic_vector (g_NUM_UPLINKS-1 downto 0);
 
     -- fec mode
-    fec_mode_i : in std_logic := '0';
+    fec_mode_i : in std_logic_vector (g_NUM_UPLINKS-1 downto 0) := (others => '0');
 
     -- bitslip flag to connect to mgt rxslide for alignment
     uplink_bitslip_o : out std_logic_vector (g_NUM_UPLINKS-1 downto 0);
@@ -263,7 +263,7 @@ begin
     --------------------------------------------------------------------------------
 
     -- Converting fec_mode_i into an integer
-    fec_sel <= 1 when fec_mode_i = '1' else 0;
+    fec_sel <= 1 when fec_mode_i(I) = '1' else 0;
 
     process (uplink_clk) is
     begin