Skip to content

Several fixes and updates for Module PCB v0 rev B

Daniel Spitzbart requested to merge modulev0b into master
  • add option to enable the power board channels, run with
ipython3 -i test_ETROC.py -- --test_chip --hard_reset --module 1 --configuration modulev0b --enable_power_board

The power board status is also added to the Module status printout (the FW version was removed because it was meaningless for the actual ETROC)

  • always list ALL modules that could be connected. --module X should be more intuitive to use now.
  • add convenience function to read Vref of the ETROC, access as etroc.read_vref()
  • hopefully fix the link stability issues seen at the FNAL setup. even the working ETROCs seem to be very sensitive to resets so we try to minimize resetting as much as possible
  • bump the FW version to 3.2.0 (includes the trigger efficiency fix)
  • disable internal Vref generation for v0 rev B boards by default
  • emulator setup should still work with the above changes, too
  • ETROC temperature readout was broken, fixed now
  • Enable/disable external trigger function as member of the RB class
  • Functionality to disable pixel readout, necessary e.g. for module 11 (bare ETROC2 module v0b). PixelMask class can be used to generate a mask, load mask in test_ETROC with --pixel_mask configs/pixel_mask_modulev0b_11.yaml
Edited by Daniel Spitzbart

Merge request reports