Start of Node integration with IPBUS

source/DataAggregator/firmware/hdl/L1DataAggregatorNode.vhd

@@ -74,6 +74,7 @@ architecture fpga of L1DataAggregatorNode is
 
   constant CHANNEL_ID : index_array := gen_channel_id(LINK_ID);
 
+  -- Conversion of DTC flags data type to DAQPath flags
   function to_daqpath_flags ( dtc_flags : tDaqFlag )
   return daqpath_flags is
     variable dqp_flags :  daqpath_flags;
@@ -84,6 +85,28 @@ architecture fpga of L1DataAggregatorNode is
     return dqp_flags;
   end function;
 
+  -- Conversion of DAQPath flags data type to DTC flags
+  function from_daqpath_flags ( dqp_flags : daqpath_flags )
+  return tDaqFlag is
+    variable dtc_flags :  tDaqFlag;
+  begin
+    dtc_flags.data_word := dqp_flags.data_word;
+    dtc_flags.event_id  := dqp_flags.event_id;
+    dtc_flags.n_words   := dqp_flags.n_words;
+    return dtc_flags;
+  end function;
+
+  -- Conversion of DTC data type to DAQPath data
+  function to_daqpath_data ( dtc_data : tDaqData )
+  return daqpath_data_in is
+    variable dqp_data :  daqpath_data_in;
+  begin
+    dqp_data.data_word := dtc_data.data_word;
+    dqp_data.event_id  := dtc_data.event_id;
+    dqp_data.n_words   := dtc_data.n_words;
+    return dqp_data;
+  end function;
+
   signal daqpath_creg                                 : ipb_reg_v(2 downto 0) := (others => (others => '0'));
   signal daqpath_sreg                                 : ipb_reg_v(2 downto 0) := (others => (others => '0'));
 
@@ -92,4 +115,13 @@ architecture fpga of L1DataAggregatorNode is
 
 begin
 
+  -- IPBUS cores
+  -- ...
+
+  -- Input port assignment
+  -- ...
+
+  -- Register assignment
+  -- ...
+
 end fpga;