Finished stub path of LinkInterfaceInternal

dtc-fe/testbenches/LinkInterfaceInternal/firmware/hdl/TestBench.vhd

@@ -19,9 +19,8 @@ architecture Behavioral of testbench is
     signal boxcar_counter : integer := 0;
 
     -- I/O streams
-    signal stream_in : lword := LWORD_NULL;
-    signal filtered_stream : lword := LWORD_NULL;
-    signal stubs     : lword := LWORD_NULL;
+    signal stubs     : ldata(1 downto 0) := (others => LWORD_NULL);
+    signal interleaved_stubs : lword := LWORD_NULL;
     
     -- Link Interface
     signal aligner_reset               : std_logic                        := '0';
@@ -58,31 +57,70 @@ begin
         end if;
     end process pReset;
 
-    -- I/O
     --==============================--
-    TestBenchIOInstance : entity work.TestBenchIO
+    CicInterface: for i in 0 to 2 - 1 generate
     --==============================--
-    generic map (
-        input_filename => "stub_extractor_output.txt",
-        output_filename => "result.txt",
-        input_line_width => 64
-    )
-    port map (
-        clk => clk_p,
-        data_out => stream_in,
-        data_in => stubs
-    );
-    pAddMetadata : process(clk_p)
+
+        signal stream_in         : lword       := LWORD_NULL;
+        signal stream_in_aligned : lword       := LWORD_NULL;
+
+        signal aligner_state : std_logic_vector(3 downto 0) := (others => '0');
+    
     begin
-        if rising_edge(clk_p) then
-            filtered_stream <= LWORD_NULL;
-            if stream_in.data /= x"0000000000000000" then
-                filtered_stream.valid <= '1';
-                filtered_stream.strobe <= '1';
-                filtered_stream.data <= stream_in.data;
-            end if;
-        end if;
-    end process pAddMetadata;
+
+        -- I/O
+        --==============================--
+        TestBenchIOInstance : entity work.TestBenchIO
+        --==============================--
+        generic map (
+            input_filename => "framed_stream.txt",
+            output_filename => "result" & integer'image(i) & ".txt",
+            input_line_width => 16
+        )
+        port map (
+            clk => clk_p,
+            data_out => stream_in,
+            data_in => stubs(i)
+        );
+
+        --==============================--
+        HeaderAligner: entity work.HeaderAligner
+        --==============================--
+        generic map (
+            module_type      => "2S",
+            bandwidth        => 5
+        )
+        port map(
+            --- Input Ports ---
+            clk              => clk_p,
+            data_in          => stream_in,
+            reset            => aligner_reset,
+            --- Output Ports ---
+            header_start     => header_start_array(i),
+            state            => aligner_state
+            -- sync_loss        => sync_loss(i)
+        );
+
+        --==============================--
+        StubExtractor: entity work.StubExtractor
+        --==============================--
+        generic map(
+            cic_index        => i,
+            module_type      => "2S",
+            bandwidth        => 5
+        )
+        port map(
+            --- Input Ports ---
+            clk              => clk_p,
+            data_in          => stream_in,
+            header_start     => header_start_array(i),
+            aligner_state    => aligner_state,
+            --- Output Ports ---
+            stub_out         => stubs(i),
+            header_out       => header_array(i)
+        );
+
+    end generate CicInterface;
 
     --==============================--
     StubInterleaver: entity work.StubInterleaver
@@ -90,10 +128,10 @@ begin
     port map(
         --- Input Ports ---
         clk           => clk_p,
-        stub_in_0     => filtered_stream,
-        stub_in_1     => filtered_stream,
+        stub_in_0     => stubs(0),
+        stub_in_1     => stubs(1),
         --- Output Ports ---
-        stub_out      => stubs
+        stub_out      => interleaved_stubs
     );
 
 end Behavioral;