Merge branch 'Merge_L1' into 'master'

Merge L1 datapath files

See merge request !78

dtc-fe/firmware/hdl/L1DataDecoder.vhd

@@ -2,13 +2,20 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
+use work.module_constants.all;
 use work.dtc_constants.all;
 
 entity L1DataDecoder is
+generic (
+     module_type : string;
+     bandwidth   : integer
+    );
+
 port (
      --- Input Ports ---
      clk                 : in std_logic;
-     data_in             : in std_logic;
+     -- Assumed data_in(0) is the latest bit arrived, so data_in is significant from left to right
+     data_in             : in std_logic_vector(cNumberOfL1ELinks(selectIndexFromModuleType(module_type, bandwidth)) - 1 downto 0);
      reset               : in std_logic;
      --- Output Ports ---
      event_number        : out std_logic_vector(cL1CtrlFifoWidth - 1 downto 0);

dtc-fe/firmware/hdl/L1DataDecoder_2S_CIC1.vhd

@@ -15,7 +15,7 @@ architecture module2SCIC1 of L1DataDecoder is
   
   signal decoder         : decoder_state := idle;
   
-  signal header          : std_logic_vector(cL1HeaderWidth - 1 downto 0)   := ( others => '0' );
+  signal header          : std_logic_vector(cL1HeaderWidth(selectIndexFromModuleType(module_type, bandwidth)) - 1 downto 0)   := ( others => '0' );
   signal payload_word    : std_logic_vector(cL1DataFifoWidth - 1 downto 0) := ( others => '0' );
   signal data            : std_logic;
   
@@ -89,7 +89,7 @@ architecture module2SCIC1 of L1DataDecoder is
           event_fifo_wr  <= '0';
           record_fifo_wr <= '0';
   
-          data <= data_in;          
+          data <= data_in(0);          
   
           case decoder is
           

dtc-fe/firmware/hdl/L1DataDecoder_2S_CIC2.vhd

@@ -15,7 +15,7 @@ type decoder_state is (idle, capture_armed, header_capture, payload_capture, sto
 
 signal decoder         : decoder_state := idle;
 
-signal header          : std_logic_vector(cL1HeaderWidth - 1 downto 0)   := ( others => '0' );
+signal header          : std_logic_vector(cL1HeaderWidth(selectIndexFromModuleType(module_type, bandwidth)) - 1 downto 0)   := ( others => '0' );
 signal payload_word    : std_logic_vector(cL1DataFifoWidth - 1 downto 0) := ( others => '0' );
 signal data            : std_logic;
 
@@ -88,7 +88,7 @@ begin
         event_fifo_wr  <= '0';
         record_fifo_wr <= '0';
 
-        data <= data_in;          
+        data <= data_in(0);          
 
         case decoder is
         
@@ -110,22 +110,22 @@ begin
           when capture_armed =>
             if data = '0' then
               decoder <= header_capture;
-              header_counter <= cL1HeaderWidth;
+              header_counter <= cL1HeaderWidth(selectIndexFromModuleType(module_type, bandwidth));
             end if;
 
           -- extract & store the header and calculate the payload length
           when header_capture =>
             -- shift in header
             header(0) <= data;
-            header(cL1HeaderWidth - 1 downto 1) <= header(cL1HeaderWidth - 2 downto 0);
+            header(cL1HeaderWidth(selectIndexFromModuleType(module_type, bandwidth)) - 1 downto 1) <= header(cL1HeaderWidth(selectIndexFromModuleType(module_type, bandwidth)) - 2 downto 0);
          
             -- wait until full length of header has been shifted in
             if header_counter = 0 then
               -- start decoding payload on next clock cycle
               decoder <= payload_capture;
               
-              status := header(cL1StatusLow + cL1StatusWidth - 1 downto cL1StatusLow);
-              l1a := header(cL1IdLow + cL1IdWidth - 1 downto cL1IdLow);
+              status := header(cL1StatusLow(selectIndexFromModuleType(module_type, bandwidth)) + cL1StatusWidth - 1 downto cL1StatusLow(selectIndexFromModuleType(module_type, bandwidth)));
+              l1a := header(cL1IdLow(selectIndexFromModuleType(module_type, bandwidth)) + cL1IdWidth - 1 downto cL1IdLow(selectIndexFromModuleType(module_type, bandwidth)));
               
               -- nclusters defines length of payload unless in unsparsified mode
               -- initialise counters for the payload_capture state

dtc-fe/firmware/hdl/L1DataDecoder_PS10G.vhd

@@ -15,17 +15,22 @@ type decoder_state is (idle, capture_armed, header_capture, payload_capture, sto
 
 signal decoder         : decoder_state := idle;
 
-signal header          : std_logic_vector(cL1HeaderWidth - 1 downto 0)   := ( others => '0' );
-signal payload_word    : std_logic_vector(cL1DataFifoWidth - 1 downto 0) := ( others => '0' );
-signal data            : std_logic;
+signal header          : std_logic_vector(cL1HeaderWidth(selectIndexFromModuleType(module_type, bandwidth))+2 downto 0)   := ( others => '0' );  
+signal payload_word    : std_logic_vector(cL1DataFifoWidth+2 downto 0) := ( others => '0' );
+signal last_word       : std_logic_vector(cL1DataFifoWidth-1 downto 0) := ( others => '0' );
 
 signal start_counter   : integer range 0 to 31 := cL1StartSequenceThresh;
-signal header_counter  : integer range 0 to 31;
+signal header_counter  : integer range -1 to 35;
 signal payload_counter : integer range -1 to 4500;
-signal bit_counter     : integer range 0 to cL1DataFifoWidth - 1;
+signal bit_counter     : integer range -1 to cL1DataFifoWidth - 1;
+signal extra_word      : std_logic := '0';
 
 signal event_counter   : unsigned(cL1CtrlFifoWidth - 1 downto 0) := to_unsigned(1, cL1CtrlFifoWidth);
-
+-- DEBUG
+signal sstatus     : std_logic_vector(cL1StatusWidth - 1 downto 0);
+signal sl1a        : std_logic_vector(cL1IdWidth - 1 downto 0);
+signal snPclusters : std_logic_vector(cL1NPcluster_width - 1 downto 0);
+signal snSclusters : std_logic_vector(CL1NScluster_width - 1 downto 0);
 
 ----
 
@@ -61,7 +66,8 @@ begin
   
     variable status     : std_logic_vector(cL1StatusWidth - 1 downto 0);
     variable l1a        : std_logic_vector(cL1IdWidth - 1 downto 0);
-    variable nclusters  : std_logic_vector(cL1NClusterWidth - 1 downto 0);
+    variable nPclusters : std_logic_vector(cL1NPcluster_width - 1 downto 0);
+    variable nSclusters : std_logic_vector(CL1NScluster_width - 1 downto 0);
   
     variable word_count : unsigned(cL1CtrlFifoWidth - 1 downto 0) := ( others => '0' );
 
@@ -88,15 +94,13 @@ begin
         event_fifo_wr  <= '0';
         record_fifo_wr <= '0';
 
-        data <= data_in;          
-
         case decoder is
         
           -- wait for a start sequence of '1's indicating the start of a packet
           when idle =>
             -- idle pattern is a repeating 10101..
-            if data = '1' then
-              start_counter <= start_counter - 1;
+            if data_in = "11" then
+              start_counter <= start_counter - 2;  -- 2 bits instead of 1 in 10G
             else
               start_counter <= cL1StartSequenceThresh;
             end if;
@@ -108,87 +112,163 @@ begin
 
           -- wait for a single '0' indicating the start of header
           when capture_armed =>
-            if data = '0' then
+            if data_in= "10" then  -- Header word starts with next two bits
               decoder <= header_capture;
-              header_counter <= cL1HeaderWidth;
+              header_counter <= cL1HeaderWidth(selectIndexFromModuleType(module_type, bandwidth));
+              header(1 downto 0) <= data_in;
+            elsif data_in(1) = '0' then  -- Header word already started
+              decoder <= header_capture;
+              header_counter <= cL1HeaderWidth(selectIndexFromModuleType(module_type, bandwidth))-1;
+              header(1 downto 0) <= data_in;
             end if;
 
           -- extract & store the header and calculate the payload length
           when header_capture =>
+          
             -- shift in header
-            header(0) <= data;
-            header(cL1HeaderWidth - 1 downto 1) <= header(cL1HeaderWidth - 2 downto 0);
-         
-            -- wait until full length of header has been shifted in
-            if header_counter = 0 then
-              -- start decoding payload on next clock cycle
+            if header_counter > 0 then
+              header(1 downto 0) <= data_in;
+              header(cL1HeaderWidth(selectIndexFromModuleType(module_type, bandwidth))+2 downto 2) <= header(cL1HeaderWidth(selectIndexFromModuleType(module_type, bandwidth)) downto 0);
+              header_counter <= header_counter - 2;  -- 2 bits instead of 1
+              
+            elsif header_counter = 0 then  -- Aligned with the end of header, the two data in bits are for payload word
+            
               decoder <= payload_capture;
               
-              status := header(cL1StatusLow + cL1StatusWidth - 1 downto cL1StatusLow);
-              l1a := header(cL1IdLow + cL1IdWidth - 1 downto cL1IdLow);
+              status := header(cL1StatusLow(selectIndexFromModuleType(module_type, bandwidth)) + cL1StatusWidth-1 downto cL1StatusLow(selectIndexFromModuleType(module_type, bandwidth)));
+              l1a := header(cL1IdLow(selectIndexFromModuleType(module_type, bandwidth)) + cL1IdWidth-1 downto cL1IdLow(selectIndexFromModuleType(module_type, bandwidth)));
+
+              -- nPclusters defines length of payload Pixels' data length
+              nPclusters := header(cL1NPcluster_low + cL1NPcluster_width-1 downto cL1NPcluster_low);
+
+              -- nSclusters defines length of payload strips' data length
+              nSclusters := header(cL1NScluster_low + cL1NScluster_width-1 downto cL1NScluster_low);
               
-              -- nclusters defines length of payload unless in unsparsified mode
-              -- initialise counters for the payload_capture state
-              if cSparsifiedMode then
-                nclusters := header(cL1NClusterLow + cL1NClusterWidth - 1 downto cL1NClusterLow);
-                -- this currently implements as a DSP - not clear if this is what we want
-                -- needs adaptation for PS data packets anyway
-                payload_counter <= to_integer(unsigned(nclusters))*cL1ClusterWidth - 1;
-              else
-                nclusters := (others=>'0');
-                payload_counter <= cL1UnsparsifiedLength - 1;
-              end if;
-                       
-              bit_counter <= cL1DataFifoWidth - 1;
-              payload_word(0) <= data;
+              --debug
+              snSclusters <= nSclusters;
+              snPclusters <= nPclusters;
+              sl1a <= l1a;
+              sstatus <= status;
+              
+              -- store the header to the data FIFO, and set word count to 1 
+              data_fifo <= l1a & status & nSclusters & nPclusters;
+              data_fifo_wr <= '1';
+              word_count := to_unsigned(1, cL1CtrlFifoWidth);
+              
+              bit_counter <= cL1DataFifoWidth - 2;
+              payload_word(1 downto 0) <= data_in;
+              payload_counter <= to_integer(unsigned(nSclusters))*cL1SClusterWidth + to_integer(unsigned(nPclusters))*cL1PClusterWidth - 2;
+              
+              
+            else  --header counter = -1 (the two new bits and the header(0) bit belong to payload word)
+              
+              decoder <= payload_capture;
+              
+              status := header(cL1StatusLow(selectIndexFromModuleType(module_type, bandwidth))+1 + cL1StatusWidth-1 downto cL1StatusLow(selectIndexFromModuleType(module_type, bandwidth))+1);
+              l1a := header(cL1IdLow(selectIndexFromModuleType(module_type, bandwidth))+1 + cL1IdWidth-1 downto cL1IdLow(selectIndexFromModuleType(module_type, bandwidth))+1);
 
-              -- store the header to the data FIFO, and set word count to 1
-              --    lowest 7 bits reserved for PS n pixel clusters
-              data_fifo <= l1a & status & nclusters & "0000000";
+              -- nPclusters defines length of payload Pixels' data length
+              nPclusters := header(cL1NPcluster_low+1 + cL1NPcluster_width-1 downto cL1NPcluster_low+1);
+
+              -- nSclusters defines length of payload strips' data length
+              nSclusters := header(cL1NScluster_low+1 + cL1NScluster_width-1 downto cL1NScluster_low+1);
+              
+              --debug
+              snSclusters <= nSclusters;
+              snPclusters <= nPclusters;
+              sl1a <= l1a;
+              sstatus <= status;
+              
+              -- store the header to the data FIFO, and set word count to 1 
+              data_fifo <= l1a & status & nSclusters & nPclusters;
               data_fifo_wr <= '1';
               word_count := to_unsigned(1, cL1CtrlFifoWidth);
-            else
-              header_counter <= header_counter - 1;
+              
+              bit_counter <= cL1DataFifoWidth - 3;
+              payload_word(2 downto 0) <= header(0) & data_in;
+              payload_counter <= to_integer(unsigned(nSclusters))*cL1SClusterWidth + to_integer(unsigned(nPclusters))*cL1PClusterWidth - 3;
+             
             end if;
 
           -- pack the payload into words until the predetermined packet length ends
           when payload_capture =>
             -- shift in payload
-            payload_word(0) <= data;
-            payload_word(cL1DataFifoWidth - 1 downto 1) <= payload_word(cL1DataFifoWidth - 2 downto 0);
+            payload_word(1 downto 0) <= data_in;
+            payload_word(cL1DataFifoWidth+2 downto 2) <= payload_word(cL1DataFifoWidth downto 0);
 
-            -- wait until full length of payload has been shifted in to leave state
-            if payload_counter <= 0 then
+            if payload_counter >0 then
+            
+              payload_counter <= payload_counter - 2;
+              
+              -- If buffer is full and all of the two previous bits belong to this data_fifo_word
+              if bit_counter = 0 then
+                data_fifo <= payload_word(cL1DataFifoWidth-1 downto 0);
+                data_fifo_wr <= '1';
+                word_count := word_count + 1;
+                bit_counter <= cL1DataFifoWidth - 2;
+                
+              -- If buffer is full and one of the previous bits received is for the next data_fifo_word
+              elsif bit_counter = -1 then 
+                data_fifo <= payload_word(cL1DataFifoWidth downto 1);
+                data_fifo_wr <= '1';
+                word_count := word_count + 1;
+                bit_counter <= cL1DataFifoWidth - 3;
+                
+              else
+                bit_counter <= bit_counter - 2;
+                
+              end if;
+            
+            
+            elsif payload_counter = 0 then  -- no bits remaining to store (all bits already in payload word buffer)
+            
               decoder <= store_event;
-            else
-              payload_counter <= payload_counter - 1;
-            end if;
-
-            -- check to see if we have packed enough data to write to data FIFO
-            if bit_counter = 0 then
-         
-              -- store the word to data FIFO, and increment word count
-              data_fifo <= payload_word;
-
-              data_fifo_wr <= '1';
-              word_count := word_count + 1;
-              bit_counter <= cL1DataFifoWidth - 1;
-            else
-              bit_counter <= bit_counter - 1;
+            
+              -- if word buffer still not full --- pad the word
+              if bit_counter >= 0 then
+                data_fifo <= std_logic_vector(unsigned(payload_word(cL1DataFifoWidth-1 downto 0)) sll bit_counter);
+                data_fifo_wr <= '1';
+                word_count := word_count + 1;
+                extra_word <= '0';
+                
+              else  -- if word buffer full
+                data_fifo <= payload_word(cL1DataFifoWidth downto 1);
+                data_fifo_wr <= '1';
+                word_count := word_count + 1;
+                extra_word <= '1';
+                last_word <= payload_word(0) & b"000" & X"0000000";
+                
+              end if;
 
-              -- check if we have reached the end of the payload, but haven't fully packed a word
-              if payload_counter = 0 then
+            else   --payload_counter = -1, only one bit of the last two bits added to payload word is good
+            
+              decoder <= store_event;
               
-                -- pad out payload word and store it to data FIFO
-                data_fifo <= std_logic_vector(unsigned(payload_word) sll bit_counter);
+              if bit_counter >= 0 then
+                data_fifo <= std_logic_vector(unsigned(payload_word(cL1DataFifoWidth-1 downto 0)) sll bit_counter);
+                data_fifo_wr <= '1';
+                word_count := word_count + 1;
+                extra_word <= '0';
+                
+              else  -- if word buffer full
+                data_fifo <= payload_word(cL1DataFifoWidth downto 1);
                 data_fifo_wr <= '1';
                 word_count := word_count + 1;
+                extra_word <= '0';
+                
               end if;
-           
+              
             end if;
 
           -- finish off packet handling by storing metadata to FIFOs, increment event counter, and reinitialise
           when store_event =>
+            
+            if (extra_word = '1') then
+              data_fifo <= last_word;
+              data_fifo_wr <= '1';
+              word_count := word_count + 1;
+            end if;
+            
             event_fifo <= std_logic_vector(event_counter);
             record_fifo <= std_logic_vector(word_count);
             event_fifo_wr <= '1';
@@ -197,6 +277,7 @@ begin
             decoder <= idle;
             word_count := (others => '0');
             event_counter <= event_counter + 1;
+            extra_word <= '0';
           
           when others =>
             decoder <= idle;

dtc-fe/firmware/hdl/L1DataDecoder_PS5G.vhd

@@ -15,14 +15,14 @@ type decoder_state is (idle, capture_armed, header_capture, payload_capture, sto
 
 signal decoder         : decoder_state := idle;
 
-signal header          : std_logic_vector(cL1HeaderWidth - 1 downto 0)   := ( others => '0' );
+signal header          : std_logic_vector(cL1HeaderWidth(selectIndexFromModuleType(module_type, bandwidth)) - 1 downto 0)   := ( others => '0' );
 signal payload_word    : std_logic_vector(cL1DataFifoWidth - 1 downto 0) := ( others => '0' );
-signal data            : std_logic;
 
 signal start_counter   : integer range 0 to 31 := cL1StartSequenceThresh;
-signal header_counter  : integer range 0 to 31;
+signal header_counter  : integer range 0 to 35;
 signal payload_counter : integer range -1 to 4500;
 signal bit_counter     : integer range 0 to cL1DataFifoWidth - 1;
+signal data            : std_logic;
 
 signal event_counter   : unsigned(cL1CtrlFifoWidth - 1 downto 0) := to_unsigned(1, cL1CtrlFifoWidth);
 
@@ -61,8 +61,9 @@ begin
   
     variable status     : std_logic_vector(cL1StatusWidth - 1 downto 0);
     variable l1a        : std_logic_vector(cL1IdWidth - 1 downto 0);
-    variable nclusters  : std_logic_vector(cL1NClusterWidth - 1 downto 0);
-  
+    variable nPclusters : std_logic_vector(cL1NPcluster_width - 1 downto 0);
+    variable nSclusters : std_logic_vector(CL1NScluster_width - 1 downto 0);
+ 
     variable word_count : unsigned(cL1CtrlFifoWidth - 1 downto 0) := ( others => '0' );
 
   begin
@@ -88,7 +89,7 @@ begin
         event_fifo_wr  <= '0';
         record_fifo_wr <= '0';
 
-        data <= data_in;          
+        data <= data_in(0);          
 
         case decoder is
         
@@ -110,47 +111,45 @@ begin
           when capture_armed =>
             if data = '0' then
               decoder <= header_capture;
-              header_counter <= cL1HeaderWidth;
+              header_counter <= cL1HeaderWidth(selectIndexFromModuleType(module_type, bandwidth));
             end if;
 
           -- extract & store the header and calculate the payload length
           when header_capture =>
             -- shift in header
             header(0) <= data;
-            header(cL1HeaderWidth - 1 downto 1) <= header(cL1HeaderWidth - 2 downto 0);
+            header(cL1HeaderWidth(selectIndexFromModuleType(module_type, bandwidth)) - 1 downto 1) <= header(cL1HeaderWidth(selectIndexFromModuleType(module_type, bandwidth)) - 2 downto 0);
          
             -- wait until full length of header has been shifted in
             if header_counter = 0 then
               -- start decoding payload on next clock cycle
               decoder <= payload_capture;
-              
-              status := header(cL1StatusLow + cL1StatusWidth - 1 downto cL1StatusLow);
-              l1a := header(cL1IdLow + cL1IdWidth - 1 downto cL1IdLow);
-              
-              -- nclusters defines length of payload unless in unsparsified mode
+              -- PS sparsified mode
+
+              status := header(cL1StatusLow(selectIndexFromModuleType(module_type, bandwidth)) + cL1StatusWidth - 1 downto cL1StatusLow(selectIndexFromModuleType(module_type, bandwidth)));
+              l1a := header(cL1IdLow(selectIndexFromModuleType(module_type, bandwidth)) + cL1IdWidth - 1 downto cL1IdLow(selectIndexFromModuleType(module_type, bandwidth)));
+
+              -- nPclusters defines length of payload Pixels' data length
+              nPclusters := header(cL1NPcluster_low + cL1NPcluster_width - 1 downto cL1NPcluster_low);
+
+              -- nSclusters defines length of payload strips' data length
+              nSclusters := header(cL1NScluster_low + cL1NScluster_width - 1 downto cL1NScluster_low);
+
               -- initialise counters for the payload_capture state
-              if cSparsifiedMode then
-                nclusters := header(cL1NClusterLow + cL1NClusterWidth - 1 downto cL1NClusterLow);
-                -- this currently implements as a DSP - not clear if this is what we want
-                -- needs adaptation for PS data packets anyway
-                payload_counter <= to_integer(unsigned(nclusters))*cL1ClusterWidth - 1;
-              else
-                nclusters := (others=>'0');
-                payload_counter <= cL1UnsparsifiedLength - 1;
-              end if;
-                       
+              -- DSP calculation? maybe too hard to calculate
+              payload_counter <= to_integer(unsigned(nSclusters))*cL1SClusterWidth + to_integer(unsigned(nPclusters))*cL1PClusterWidth - 1;
+
               bit_counter <= cL1DataFifoWidth - 1;
               payload_word(0) <= data;
 
-              -- store the header to the data FIFO, and set word count to 1
-              --    lowest 7 bits reserved for PS n pixel clusters
-              data_fifo <= l1a & status & nclusters & "0000000";
+              -- store the header to the data FIFO, and set word count to 1 
+              data_fifo <= l1a & status & nSclusters & nPclusters;
               data_fifo_wr <= '1';
               word_count := to_unsigned(1, cL1CtrlFifoWidth);
             else
               header_counter <= header_counter - 1;
             end if;
-
+              
           -- pack the payload into words until the predetermined packet length ends
           when payload_capture =>
             -- shift in payload

dtc-fe/firmware/hdl/L1DataExtractor.vhd

@@ -20,7 +20,7 @@ entity L1DataExtractor is
     port (
 	    --- Input Ports ---
         clk                 : in std_logic;
-        data_in             : in std_logic;
+        data_in             : in std_logic_vector(cNumberOfL1ELinks(selectIndexFromModuleType(module_type, bandwidth))-1 downto 0);
         daq_ipb_ctrl        : in std_logic_vector(31 downto 0);
         daq_fifo_read       : in tDaqFlag;
         --- Output Ports ---
@@ -86,6 +86,10 @@ begin
       --==============================--
       L1DataDecoder: entity work.L1DataDecoder(module2SCIC1)
       --==============================--
+      generic map (
+        module_type      => module_type,
+        bandwidth        => bandwidth
+    )  
       port map (
           --- Input Ports ---
           clk            => clk,
@@ -105,6 +109,10 @@ begin
       --==============================--
       L1DataDecoder: entity work.L1DataDecoder(module2SCIC2)
       --==============================--
+      generic map (
+        module_type      => module_type,
+        bandwidth        => bandwidth
+    )
       port map (
           --- Input Ports ---
           clk            => clk,
@@ -128,6 +136,10 @@ begin
       --==============================--
       L1DataDecoder: entity work.L1DataDecoder(modulePS5G)
       --==============================--
+      generic map (
+        module_type      => module_type,
+        bandwidth        => bandwidth
+    )
       port map (
           --- Input Ports ---
           clk            => clk,
@@ -147,6 +159,10 @@ begin
       --==============================--
       L1DataDecoder: entity work.L1DataDecoder(modulePS10G)
       --==============================--
+      generic map (
+        module_type      => module_type,
+        bandwidth        => bandwidth
+    )
       port map (
           --- Input Ports ---
           clk            => clk,

dtc-fe/firmware/hdl/LinkInterface.vhd

@@ -150,8 +150,8 @@ CicInterface: for i in 0 to cNumberOfCICs - 1 generate
 
     signal stream_in         : lword       := LWORD_NULL;
     signal stream_in_aligned : lword       := LWORD_NULL;
-    
-    signal l1_data_in        : std_logic   := '0';
+
+    signal l1_data_in        : std_logic_vector(cNumberOfL1ELinks(selectIndexFromModuleType(module_type, bandwidth)) -1 downto 0)   := (Others=>'0'); 
     signal aligner_reset     : std_logic   := '0';
   
 begin
@@ -160,8 +160,7 @@ begin
     stream_in.strobe                             <= link_in.data(32*i + 31);
     stream_in.data(cNumberOfELinks(selectIndexFromModuleType(module_type, bandwidth)) - 1 downto 0) <= link_in.data(32*i + cNumberOfELinks(selectIndexFromModuleType(module_type, bandwidth)) - 1 downto 32*i);
     
-    l1_data_in                                   <= link_in.data(32*i + cNumberOfELinks(selectIndexFromModuleType(module_type, bandwidth)));
-   
+    l1_data_in                                   <= link_in.data(32*i + cNumberOfELinks(selectIndexFromModuleType(module_type, bandwidth)) + cNumberOfL1ELinks(selectIndexFromModuleType(module_type, bandwidth))-1 downto 32*i + cNumberOfELinks(selectIndexFromModuleType(module_type, bandwidth))); 
     aligner_reset                                <= fe_control_registers(0)(i);
 
     -- --==============================--

dtc-fe/firmware/hdl/module_constants.vhd

@@ -19,6 +19,7 @@ package module_constants is
 
     constant cGBTFrameWidth           : integer                     := 112;
     constant cNumberOfELinks          : tModuleConstantIntegerArray := (5, 6, 12);
+    constant cNumberOfL1ELinks        : tModuleConstantIntegerArray := (1, 1, 2);
 
     constant cStubWidth               : tModuleConstantIntegerArray := (18, 21, 21);
     constant cHeaderWidth             : integer                     := 28;
@@ -38,16 +39,23 @@ package module_constants is
     constant cAlignmentDepth          : integer                     := 8; -- Can be reduced if no realignment is necessary, reducing both latency and resource usage for the FrameAligner
     
     constant cL1StartSequenceThresh   : integer                     := 20;
-    constant cL1HeaderWidth           : integer                     := 18;
+    constant cL1HeaderWidth           : tModuleConstantIntegerArray := (18, 33, 33);
+    constant cL1PClusterWidth         : integer                     := 17;
+    constant cL1SClusterWidth         : integer                     := 14;
     constant cL1ClusterWidth          : integer                     := 14;
-    
+
     constant cL1StatusWidth           : integer                     := 9;
-    constant cL1StatusLow             : integer                     := 9;
+    constant cL1StatusLow             : tModuleConstantIntegerArray := (9, 24, 24);
     constant cL1IdWidth               : integer                     := 9;
-    constant cL1IdLow                 : integer                     := 0;
+    constant cL1IdLow                 : tModuleConstantIntegerArray := (0, 15, 15);
+    constant cL1NPcluster_width       : integer                     := 7;
+    constant cL1NPcluster_low         : integer                     := 0;
+    constant cL1NScluster_width       : integer                     := 7;
+    constant cL1NScluster_low         : integer                     := 8;
     constant cL1NClusterWidth         : integer                     := 7;
     constant cL1NClusterLow           : integer                     := 1;
-    
+
+ 
     constant cSparsifiedMode          : boolean                     := false;
     constant cL1UnsparsifiedLength    : integer                     := 2200;
 
@@ -90,4 +98,4 @@ package body module_constants is
         return index;
     end selectIndexFromModuleType;
 
-end package body module_constants;
\ No newline at end of file
+end package body module_constants;