Added LinkInterface internal

dtc-fe/testbenches/LinkInterfaceInternal/firmware/cfg/top.dep

+setup --cd ../ucf sim.tcl
+
+src TestBench.vhd
+src -c sim/common TestBenchIO.vhd
+
+src LinkInterfaceInternal.vhd
+
+src -c dtc-fe StubConverter.vhd
+src -c dtc-fe StubInterleaver.vhd
+
+src -c dtc-fe StubExtractor.vhd
+src -c dtc-fe HeaderExtractor_2S.vhd
+src -c dtc-fe HeaderExtractor_PS5G.vhd
+src -c dtc-fe HeaderExtractor_PS10G.vhd
+src -c dtc-fe HeaderExtractor.vhd
+
+src -c dtc-fe HeaderAligner.vhd
+src -c dtc-fe HeaderFingerprintChecker_2S.vhd
+src -c dtc-fe HeaderFingerprintChecker_PS10G.vhd
+src -c dtc-fe HeaderFingerprintChecker_PS5G.vhd
+src -c dtc-fe HeaderFingerprintChecker.vhd
+
+src -c dtc-fe data_types.vhd
+src -c dtc-fe module_constants.vhd
+
+src -c dtc-be/common data_types.vhd
+src -c dtc-be/common dtc_constants.vhd
+src -c emp-fwk:components/datapath emp_data_types.vhd
+
+@device_generation = "UltraScalePlus"
+@device_name = "xcku15p"
+@device_package = "-ffva1760"
+@device_speed = "-2-e"
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dtc-fe/testbenches/LinkInterfaceInternal/firmware/hdl/LinkInterfaceInternal.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.emp_data_types.all;
+
+use work.module_constants.all;
+use work.front_end_data_types.all;
+use work.dtc_constants.all;
+use work.dtc_data_types.all;
+
+
+entity LinkInterfaceInternal is
+generic (
+    module_type : string;
+    bandwidth   : integer;
+    cic_type    : string;
+    enable_monitoring : boolean := true;
+    emp_channel : integer := 0
+);
+port (
+    --- Input Ports ---
+    clk_p            : in  std_logic;
+    clk40            : in  std_logic;
+    link_in          : in  lword := LWORD_NULL;
+    aligner_reset    : in std_logic;
+    --- Output Ports ---
+    stub_out         : out lword := LWORD_NULL;
+    header_out       : out tCICHeaderArray(cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
+    --- Debug Ports ---
+    debug_header_start  : out std_logic_vector(1 downto 0);
+    debug_header_match  : out std_logic_vector(1 downto 0);
+    debug_aligner_state : out std_logic_vector(7 downto 0)
+);
+end LinkInterfaceInternal;
+
+architecture rtl of LinkInterfaceInternal is
+
+    -- Link decoding and module readout
+
+    signal headers                  : tCICHeaderArray(cNumberOfCICs - 1 downto 0) := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
+    signal stubs                    : ldata(cNumberOfCICs - 1 downto 0) := (others => LWORD_NULL);
+    signal stubs_interleaved        : lword                             := LWORD_NULL;
+
+    signal aligner_state            : tAlignerArray(cNumberOfCICs - 1 downto 0)    := (others => (others => '0'));
+    signal header_start             : std_logic_vector(cNumberOfCICs - 1 downto 0) := (others => '0');
+    signal sync_loss                : std_logic_vector(cNumberOfCICs - 1 downto 0) := (others => '0');
+
+
+
+begin
+
+
+    header_out          <= headers;
+
+    debug_header_start  <= header_start;
+    debug_header_match  <= sync_loss;
+    debug_aligner_state <= aligner_state(1) & aligner_state(0);
+
+
+
+    --==============================--
+    -- Link decoding and module readout
+    --==============================--
+
+
+    --==============================--
+    CicInterface: for i in 0 to cNumberOfCICs - 1 generate
+    --==============================--
+
+        constant module_type_index : integer := selectIndexFromModuleType(module_type, bandwidth);
+
+        signal stream_in         : lword       := LWORD_NULL;
+        signal stream_in_aligned : lword       := LWORD_NULL;
+
+        signal l1_data_in        : std_logic_vector(cNumberOfL1ELinks(module_type_index) -1 downto 0)   := (Others=>'0'); 
+    
+    begin
+
+        stream_in.valid                              <= link_in.valid;
+        stream_in.strobe                             <= '1';
+        stream_in.data(cNumberOfELinks(module_type_index) - 1 downto 0) <= link_in.data(32*i + cNumberOfELinks(module_type_index) - 1 downto 32*i);
+        
+        l1_data_in                                   <= link_in.data(32*i + cNumberOfELinks(module_type_index) + cNumberOfL1ELinks(module_type_index)-1 downto 32*i + cNumberOfELinks(module_type_index)); 
+
+        --==============================--
+        HeaderAligner: entity work.HeaderAligner
+        --==============================--
+        generic map (
+            module_type      => module_type,
+            bandwidth        => bandwidth
+        )
+        port map(
+            --- Input Ports ---
+            clk              => clk_p,
+            data_in          => stream_in,
+            reset            => aligner_reset,
+            --- Output Ports ---
+            header_start     => header_start(i),
+            state            => aligner_state(i),
+            sync_loss        => sync_loss(i)
+        );
+
+        --==============================--
+        StubExtractor: entity work.StubExtractor
+        --==============================--
+        generic map(
+            cic_index        => i,
+            module_type      => module_type,
+            bandwidth        => bandwidth
+        )
+        port map(
+            --- Input Ports ---
+            clk              => clk_p,
+            data_in          => stream_in,
+            header_start     => header_start(i),
+            aligner_state    => aligner_state(i),
+            --- Output Ports ---
+            stub_out         => stubs(i),
+            header_out       => headers(i)
+        );
+
+    end generate CicInterface;
+
+
+    --==============================--
+    -- Stub interleaving
+    --==============================--
+
+    --==============================--
+    StubInterleaver: entity work.StubInterleaver
+    --==============================--
+    port map(
+        --- Input Ports ---
+        clk           => clk_p,
+        stub_in_0     => stubs(0),
+        stub_in_1     => stubs(0),
+        --- Output Ports ---
+        stub_out      => stubs_interleaved
+    );
+
+
+    --==============================--
+    -- Stub conversion for input to router
+    --==============================--
+
+    --==============================--
+    StubConverter: entity work.StubConverter
+    --==============================--
+    generic map (
+        module_type => module_type,
+        bandwidth   => bandwidth
+    )
+    port map(
+        --- Input Ports ---
+        clk           => clk_p,
+        stub_in       => stubs_interleaved,
+        --- Output Ports ---
+        stub_out      => stub_out
+    );
+
+
+end rtl;

dtc-fe/testbenches/LinkInterfaceInternal/firmware/hdl/TestBench.vhd

+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+use work.emp_data_types.all;
+use work.dtc_data_types.all;
+
+entity testbench is
+end testbench;
+
+architecture Behavioral of testbench is
+
+    -- Clocks
+    signal clk_p : std_logic := '0';
+    signal clk40 : std_logic := '0';
+
+    -- Counters
+    signal global_counter : integer := 0;
+    signal boxcar_counter : integer := 0;
+
+    -- I/O streams
+    signal stream_in : lword := LWORD_NULL;
+    signal filtered_stream : lword := LWORD_NULL;
+    signal stubs     : lword := LWORD_NULL;
+    
+    -- Link Interface
+    signal aligner_reset               : std_logic                        := '0';
+    signal header_start_array          : std_logic_vector(2 - 1 downto 0) := (others => '0');
+    signal header_start_array_buffered : std_logic_vector(2 - 1 downto 0) := (others => '0');
+    signal header_array                : tCICHeaderArray(2 - 1 downto 0)  := (others => ('0', (others => '0'), (others => '0'), (others => '0')));
+
+begin
+
+    -- Clocks
+    clk_p <= not clk_p after 3.125 ns;
+    clk40 <= not clk40 after 25 ns;
+
+    -- Counters
+    pIncrementCounter : process(clk_p)
+    begin
+        if rising_edge(clk_p) then
+            global_counter <= global_counter + 1;
+
+            if header_start_array(0) = '1' then
+                boxcar_counter <= boxcar_counter + 1;
+            end if;
+        end if;
+    end process pIncrementCounter;
+
+    -- Resets
+    pReset : process(clk_p)
+    begin
+        if rising_edge(clk_p) then
+            aligner_reset <= '0';
+            if global_counter = 10 then
+                aligner_reset <= '1';
+            end if;
+        end if;
+    end process pReset;
+
+    -- I/O
+    --==============================--
+    TestBenchIOInstance : entity work.TestBenchIO
+    --==============================--
+    generic map (
+        input_filename => "stub_extractor_output.txt",
+        output_filename => "result.txt",
+        input_line_width => 64
+    )
+    port map (
+        clk => clk_p,
+        data_out => stream_in,
+        data_in => stubs
+    );
+    pAddMetadata : process(clk_p)
+    begin
+        if rising_edge(clk_p) then
+            filtered_stream <= LWORD_NULL;
+            if stream_in.data /= x"0000000000000000" then
+                filtered_stream.valid <= '1';
+                filtered_stream.strobe <= '1';
+                filtered_stream.data <= stream_in.data;
+            end if;
+        end if;
+    end process pAddMetadata;
+
+    --==============================--
+    StubInterleaver: entity work.StubInterleaver
+    --==============================--
+    port map(
+        --- Input Ports ---
+        clk           => clk_p,
+        stub_in_0     => filtered_stream,
+        stub_in_1     => filtered_stream,
+        --- Output Ports ---
+        stub_out      => stubs
+    );
+
+end Behavioral;

dtc-fe/testbenches/LinkInterfaceInternal/firmware/ucf/sim.tcl

+set_property top testbench [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+update_compile_order -fileset sources_1
+set_property source_mgmt_mode DisplayOnly [current_project]
+
+import_files -fileset sim_1 -norecurse ../../src/dtc/dtc-fe/testbenches/LinkInterfaceInternal/stub_extractor_output.txt
+import_files -fileset sim_1 -norecurse ../../src/dtc/dtc-fe/testbenches/LinkInterfaceInternal/framed_stream.txt
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