Added StubInterleaver input

dtc-fe/testbenches/StubExtractor/firmware/hdl/TestBench.vhd

@@ -58,12 +58,13 @@ begin
     --==============================--
     generic map (
         input_filename => "framed_stream.txt",
-        output_filename => "result.txt"
+        output_filename => "result.txt",
+        output_line_width => 64
     )
     port map (
         clk => clk_p,
-        data_out => stream_in
-        -- data_in => stubs
+        data_out => stream_in,
+        data_in => stubs
     );
 
     --==============================--
@@ -97,9 +98,9 @@ begin
         clk              => clk_p,
         data_in          => stream_in,
         header_start     => header_start,
-        aligner_state    => aligner_state
+        aligner_state    => aligner_state,
         --- Output Ports ---
-        -- stub_out         => stubs(i),
+         stub_out         => stubs
         -- header_out       => headers(i)
     );
 

dtc-fe/testbenches/StubInterleaver/firmware/cfg/top.dep

 setup --cd ../ucf sim.tcl
 
 src TestBench.vhd
+src -c sim/common TestBenchIO.vhd
 
 src -c dtc-fe StubInterleaver.vhd
 

dtc-fe/testbenches/StubInterleaver/firmware/hdl/TestBench.vhd

@@ -20,6 +20,7 @@ architecture Behavioral of testbench is
 
     -- I/O streams
     signal stream_in : lword := LWORD_NULL;
+    signal filtered_stream : lword := LWORD_NULL;
     signal stubs     : lword := LWORD_NULL;
     
     -- Link Interface
@@ -57,4 +58,42 @@ begin
         end if;
     end process pReset;
 
+    -- I/O
+    --==============================--
+    TestBenchIOInstance : entity work.TestBenchIO
+    --==============================--
+    generic map (
+        input_filename => "stub_extractor_output.txt",
+        output_filename => "result.txt",
+        input_line_width => 64
+    )
+    port map (
+        clk => clk_p,
+        data_out => stream_in,
+        data_in => stubs
+    );
+    pAddMetadata : process(clk_p)
+    begin
+        if rising_edge(clk_p) then
+            filtered_stream <= LWORD_NULL;
+            if stream_in.data /= x"0000000000000000" then
+                filtered_stream.valid <= '1';
+                filtered_stream.strobe <= '1';
+                filtered_stream.data <= stream_in.data;
+            end if;
+        end if;
+    end process pAddMetadata;
+
+    --==============================--
+    StubInterleaver: entity work.StubInterleaver
+    --==============================--
+    port map(
+        --- Input Ports ---
+        clk           => clk_p,
+        stub_in_0     => filtered_stream,
+        stub_in_1     => filtered_stream,
+        --- Output Ports ---
+        stub_out      => stubs
+    );
+
 end Behavioral;

dtc-fe/testbenches/StubInterleaver/firmware/ucf/sim.tcl

 set_property top testbench [get_filesets sim_1]
-set_property top_lib xil_defaultlib [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
\ No newline at end of file
+update_compile_order -fileset sources_1
+set_property source_mgmt_mode DisplayOnly [current_project]
+
+import_files -fileset sim_1 -norecurse ../../src/dtc/dtc-fe/testbenches/StubInterleaver/stub_extractor_output.txt
\ No newline at end of file