Resolve "Provide module information to software as IPBus register"

dtc-fe/addr_table/dtc_link_fectrl.xml

-<node description="Link interface channel control" fwinfo="endpoint;width=0">
+<node description="Link interface channel control" fwinfo="endpoint;width=1">
     <node id="aligner_reset0" address="0x0" mask="0x0001"/>
     <node id="aligner_reset1" address="0x0" mask="0x0002"/>
     <node id="counter_reset"  address="0x0" mask="0x0004"/>
+    <node id="emp_channel"    address="0x1"/>
 </node>

dtc-fe/firmware/hdl/LinkInterface.vhd

@@ -20,7 +20,8 @@ entity LinkInterface is
 generic (
     module_type : string;
     bandwidth   : integer;
-    cic_type    : string
+    cic_type    : string;
+    emp_channel : integer := 0
 );
 port (
     --- Input Ports ---
@@ -56,6 +57,7 @@ signal ipb_to_slaves            : ipb_wbus_array(N_SLAVES - 1 downto 0);
 signal ipb_from_slaves          : ipb_rbus_array(N_SLAVES - 1 downto 0);
 
 signal fe_control_registers     : ipb_reg_v(0 downto 0) := (others => (others => '0'));
+signal fe_status_registers      : ipb_reg_v(0 downto 0) := (others => (others => '0'));
 
 signal daq_status_registers     : ipb_reg_v(5 downto 0) := (others => (others => '0'));
 signal daq_control_registers    : ipb_reg_v(1 downto 0) := (others => (others => '0'));
@@ -81,6 +83,7 @@ header_out          <= headers;
 debug_header_start  <= header_start;
 debug_header_match  <= sync_loss;
 debug_aligner_state <= aligner_state(1) & aligner_state(0);
+fe_status_registers(0) <= std_logic_vector(to_unsigned(emp_channel, 32));
 
 
 --==============================--
@@ -107,13 +110,14 @@ fe_control: entity work.ipbus_ctrlreg_v
 --==============================--
 generic map(
     N_CTRL            => 1,
-    N_STAT            => 0
+    N_STAT            => 1
 )
 port map(
     clk               => clk,
     reset             => rst,
     ipbus_in          => ipb_to_slaves(N_SLV_FE_CTRL),
     ipbus_out         => ipb_from_slaves(N_SLV_FE_CTRL),
+    d                 => fe_status_registers,
     q		          => fe_control_registers
 );
 

top/dtc-mini/common/firmware/hdl/emp_payload.vhd

@@ -172,7 +172,8 @@ begin
         generic map (
             module_type => cDTCInputLinkMap(i).module_type,
             bandwidth   => cDTCInputLinkMap(i).bandwidth,
-            cic_type    => cDTCInputLinkMap(i).cic_type
+            cic_type    => cDTCInputLinkMap(i).cic_type,
+            emp_channel => cDTCInputLinkMap(i).index
         )
         port map (
             --- Input Ports ---