bypass trigger rate is ~600Hz

common/firmware/hdl/EcalDataFilter.vhd

@@ -35,6 +35,8 @@ architecture rtl of EcalDataFilter is
   signal regs              : ipb_reg_v(32 downto 0) := (others => (others => '0'));
 
   signal bypass_s          : std_logic;
+  signal b_trg             : std_logic;
+	signal b_counter         : std_logic_vector(15 downto 0);
 
   signal data_s            : std_logic_vector(28 * 16 -1 downto 0);
   signal data_clk40        : std_logic_vector(28 * 16 -1 downto 0);
@@ -78,7 +80,7 @@ begin
   end generate;
 
   trig_o_lat <= zs_valid_lat when bypass_s = '0' else "000011";
-  trig_o     <= trig40       when bypass_s = '0' else x"c0000001";
+  trig_o     <= trig40       when bypass_s = '0' else x"c000000" & "000" & b_trg;
   -- trig_o     <= trig_sync    when bypass_s = '0' else x"c0000001";
 
   --data_in_proc : process(clk_p)
@@ -111,7 +113,15 @@ begin
   begin
    if reset = '1' then
      trig40 <= (others => '0');
+		 b_counter <= (others => '0');
    elsif rising_edge(clk40) then
+
+		 b_counter <= std_logic_vector(unsigned(b_counter) + 1);
+		 b_trg <= '0';
+		 if (b_counter = x"0000") then
+			 b_trg <= '1';
+	   end if;
+
      zs_valid_p(0) <= zs_valid;
      zs_valid_p(1) <= zs_valid_p(0);
      zs_all_valids_p0 <= zs_all_valids;