Update top/firmware/hdl/link_maps.vhd, top/firmware/hdl/emp_payload.vhd

top/firmware/hdl/emp_payload.vhd

@@ -236,7 +236,7 @@ begin
 end generate;
 
 
-linkor.data(63 downto 0) <= linksout(0).data(63 downto 0) or linksout(1).data(63 downto 0) or linksout(2).data(63 downto 0) or linksout(3).data(63 downto 0); --or linksout(4).data(63 downto 0) or linksout(5).data(63 downto 0);
+linkor.data(63 downto 0) <= linksout(0).data(63 downto 0) or linksout(1).data(63 downto 0) or linksout(2).data(63 downto 0) or linksout(3).data(63 downto 0) or linksout(4).data(63 downto 0) or linksout(5).data(63 downto 0) or linksout(6).data(63 downto 0) or linksout(7).data(63 downto 0);
 
 --==============================--
 genHack: for i in 0 to cNumberOfFEModules - 1 generate

top/firmware/hdl/link_maps.vhd

@@ -3,11 +3,11 @@ use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
 package dtc_link_maps is
-    constant cNumberOfFEModules   : integer := 4;
+    constant cNumberOfFEModules   : integer := 8;
     constant cNumberOfOutputLinks : integer := 4;
 
     type tDTCInputLinkMap is array(0 to cNumberOfFEModules - 1) of integer;
-    constant cDTCInputLinkMap     : tDTCInputLinkMap := (8, 9, 10, 11);
+    constant cDTCInputLinkMap     : tDTCInputLinkMap := (8, 9, 10, 11, 12, 13, 14, 15);
 
     type tDTCOutputLinkMap is array(0 to cNumberOfOutputLinks - 1) of integer;
     constant cDTCOutputLinkMap    : tDTCOutputLinkMap := (16, 17, 18, 19);