last flag is initialized

common/firmware/hdl/EcalDataProcessor.vhd

@@ -206,6 +206,7 @@ begin
           data_out(0).data  <= (others => '0');
           data_out(0).valid <= '0';
           data_out(0).start <= '0';
+          data_out(0).last <= '0';
           data_out(0).strobe <= '0';
           ostate <= wait_start;
         elsif rising_edge(clk_p) then
@@ -213,6 +214,7 @@ begin
           data_out(0).data  <= data_out_s.data;
           data_out(0).valid <= '0';
           data_out(0).start <= '0';
+          data_out(0).last <= '0';
           data_out(0).strobe <= '0';
           case ostate is
             when wait_start =>