Update top/firmware/hdl/emp_project_decl.vhd, top/firmware/hdl/link_maps.vhd,...

Update top/firmware/hdl/emp_project_decl.vhd, top/firmware/hdl/link_maps.vhd, top/firmware/hdl/emp_payload.vhd

top/firmware/hdl/emp_payload.vhd

@@ -236,7 +236,7 @@ begin
 end generate;
 
 
-linkor.data(63 downto 0) <= linksout(0).data(63 downto 0) or linksout(1).data(63 downto 0) or linksout(2).data(63 downto 0) or linksout(3).data(63 downto 0) or linksout(4).data(63 downto 0) or linksout(5).data(63 downto 0) or linksout(6).data(63 downto 0) or linksout(7).data(63 downto 0) or linksout(8).data(63 downto 0) or linksout(9).data(63 downto 0) or linksout(10).data(63 downto 0) or linksout(11).data(63 downto 0) or linksout(12).data(63 downto 0) or linksout(13).data(63 downto 0) or linksout(14).data(63 downto 0) or linksout(15).data(63 downto 0);
+linkor.data(63 downto 0) <= linksout(0).data(63 downto 0) or linksout(1).data(63 downto 0) or linksout(2).data(63 downto 0) or linksout(3).data(63 downto 0) or linksout(4).data(63 downto 0) or linksout(5).data(63 downto 0) or linksout(6).data(63 downto 0) or linksout(7).data(63 downto 0) or linksout(8).data(63 downto 0) or linksout(9).data(63 downto 0) or linksout(10).data(63 downto 0) or linksout(11).data(63 downto 0) or linksout(12).data(63 downto 0) or linksout(13).data(63 downto 0) or linksout(14).data(63 downto 0) or linksout(15).data(63 downto 0) or linksout(16).data(63 downto 0) or linksout(17).data(63 downto 0) or linksout(18).data(63 downto 0) or linksout(19).data(63 downto 0);
 
 --==============================--
 genHack: for i in 0 to cNumberOfFEModules - 1 generate

top/firmware/hdl/emp_project_decl.vhd

@@ -36,7 +36,7 @@ package emp_project_decl is
     1  => (lpgbt, buf, no_fmt, buf, lpgbt),   --Bank 226
     2  => (lpgbt, buf, no_fmt, buf, lpgbt),   --Bank 227
     3  => (lpgbt, buf, no_fmt, buf, lpgbt),   --Bank 228
-    4  => (no_mgt, buf, no_fmt, buf, no_mgt),   --Bank 229
+    4  => (lpgbt, buf, no_fmt, buf, lpgbt),   --Bank 229
     5  => (no_mgt, buf, no_fmt, buf, no_mgt),   --Bank 230
     6  => (no_mgt, buf, no_fmt, buf, no_mgt),   --Bank 231
     7  => (no_mgt, buf, no_fmt, buf, no_mgt),   --Bank 232
@@ -62,6 +62,7 @@ package emp_project_decl is
     1 => ( 0=>(false, true, 0, false), 1=>(false, true, 0, false), 2=>(false, true, 0, false), 3=>(false, true, 0, false)),
     2 => ( 0=>(false, true, 0, false), 1=>(false, true, 0, false), 2=>(false, true, 0, false), 3=>(false, true, 0, false)),
     3 => ( 0=>(false, true, 0, false), 1=>(false, true, 0, false), 2=>(false, true, 0, false), 3=>(false, true, 0, false)),
+    4 => ( 0=>(false, true, 0, false), 1=>(false, true, 0, false), 2=>(false, true, 0, false), 3=>(false, true, 0, false)),
     others => kDummyRegionDataFramer
   );
 
@@ -71,6 +72,7 @@ package emp_project_decl is
     1  => (FEC5, DATARATE_5G12, PCS),
     2  => (FEC5, DATARATE_5G12, PCS),
     3  => (FEC5, DATARATE_5G12, PCS),
+    4  => (FEC5, DATARATE_5G12, PCS),
     others => kDummyRegionLpgbt
   );
 

top/firmware/hdl/link_maps.vhd

@@ -3,11 +3,11 @@ use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
 
 package dtc_link_maps is
-    constant cNumberOfFEModules   : integer := 16;
+    constant cNumberOfFEModules   : integer := 20;
     constant cNumberOfOutputLinks : integer := 4;
 
     type tDTCInputLinkMap is array(0 to cNumberOfFEModules - 1) of integer;
-    constant cDTCInputLinkMap     : tDTCInputLinkMap := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
+    constant cDTCInputLinkMap     : tDTCInputLinkMap := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19);
 
     type tDTCOutputLinkMap is array(0 to cNumberOfOutputLinks - 1) of integer;
     constant cDTCOutputLinkMap    : tDTCOutputLinkMap := (16, 17, 18, 19);