Added register for user bits

top/addr_table/emp_payload.xml

@@ -12,10 +12,13 @@
     <node id="link_monitor" address="0x10000" module="file://LinkMonitorInterface.xml"/>
 
     <node id="mprocessor" address="0x40000" description="MProcessor control and status" module="file://mprocessor.xml" fwinfo="endpoint;width=12"/>
-    <node id="mproc_ctrl" address="0x4ffff" description="MProcessor channel control" fwinfo="endpoint;width=0">
-        <node id="chan_sel" mask="0x7f"/>
-        <node id="srst"     mask="0x80"/>
-        <node id="sync_fastreset"     mask="0x100"/>
+    <node id="mproc_ctrl" address="0x4fff0" description="MProcessor channel control" fwinfo="endpoint;width=1">
+        <node id="control" address="0x0">
+            <node id="chan_sel" mask="0x7f"/>
+            <node id="srst"     mask="0x80"/>
+            <node id="sync_fastreset"     mask="0x100"/>
+        </node>
+        <node id="header_user_bits" address="0x1"/>
     </node>
     
     <node id="be_daq" address="0x40000000" module="file://dtc_data_aggregator.xml" fwinfo="endpoint;width=30"/>

top/firmware/hdl/emp_payload.vhd

@@ -60,7 +60,8 @@ architecture rtl of emp_payload is
 
     signal fe_control_registers         : ipb_reg_v(0 downto 0);
     signal fe_status_registers          : ipb_reg_v(0 downto 0);
-    signal mproc_channel_sel            : ipb_reg_v(0 downto 0);
+    signal mproc_control_registers      : ipb_reg_v(1 downto 0);
+    signal mproc_status_registers       : ipb_reg_v(0 downto 0);
     signal link_aggr_control            : ipb_reg_v(0 downto 0);
 
 
@@ -159,18 +160,17 @@ begin
     );
 
     --==============================--
-    mproc_channel_ctrl: entity work.ipbus_reg_v
+    mproc_ctrl: entity work.ipbus_ctrlreg_v
     --==============================--
     generic map(
-        N_REG           => 1
+        N_CTRL    => 2
     )
     port map(
         clk             => clk,
         reset           => rst,
         ipbus_in        => ipb_to_slaves(N_SLV_MPROC_CTRL),
         ipbus_out       => ipb_from_slaves(N_SLV_MPROC_CTRL),
-        q               => mproc_channel_sel,
-        qmask           => (0 => X"00000fff")
+        q		        => mproc_control_registers
     );
 
 
@@ -341,7 +341,7 @@ begin
     port map(
         clk             => clk,
         rst             => rst,
-        sel             => mproc_channel_sel(0)(6 downto 0),
+        sel             => mproc_control_registers(0)(6 downto 0),
         ipb_in          => ipb_to_slaves(N_SLV_MPROCESSOR),
         ipb_out         => ipb_from_slaves(N_SLV_MPROCESSOR),
         ipbdc_out       => mprocessor_ipb_chain(0),
@@ -413,7 +413,7 @@ begin
         readout_reset => readout_reset(0),
         header_start => header_start_array_buffered(0),
         module_header_in => header_array,
-        user_bits => x"d451d007",
+        user_bits => mproc_control_registers(1),
         --- Ouput Ports ---
         header_out => payload_headers
     );
@@ -464,8 +464,8 @@ begin
         end if;
     end process;
 
-    ttc_resync_reset <= mproc_channel_sel(0)(8);
-    srst <= mproc_channel_sel(0)(7) or ttc_oc0;
+    ttc_resync_reset <= mproc_control_registers(0)(8);
+    srst <= mproc_control_registers(0)(7) or ttc_oc0;
 
     q(4).valid  <= '1';
     q(4).data   <= "0000" & std_logic_vector(bunch_counter) & "0000000000000000" & std_logic_vector(orbit_counter);