added on more pipeline for bcid check

common/firmware/hdl/EcalDataAggregator.vhd

@@ -26,7 +26,7 @@ architecture rtl of EcalDataAggregator is
   signal ecal_data_reg               : std_logic_vector(28 * 16 -1 downto 0);
   signal valid_reg                   : std_logic := '0';
   
-  type tBcIdPipe is array (integer range 0 to 7) of std_logic_vector(11 downto 0);
+  type tBcIdPipe is array (integer range 0 to 8) of std_logic_vector(11 downto 0);
   signal bcid_p : tBcIdPipe;
   
 begin
@@ -57,7 +57,7 @@ begin
         if rising_edge(clk_p) then
           
           bcid_p(0) <= bcid;
-          for i in 0 to 6 loop
+          for i in 0 to 7 loop
             bcid_p(i+1) <= bcid_p(i);
           end loop;
                    
@@ -78,7 +78,7 @@ begin
             data_out(0).start <= '1';         
           end if;
                     
-         if unsigned(bcid) = unsigned(bcid_p(7)) + 1 or (unsigned(bcid) = 0 and unsigned(bcid_p(7)) = 3563) then
+         if unsigned(bcid_p(0)) = unsigned(bcid_p(8)) + 1 or (unsigned(bcid_p(0)) = 0 and unsigned(bcid_p(8)) = 3563) then
             timer := 0;
             ecal_data_reg <= ecal_data;
             valid_reg <= '1';