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Commit 7567b0ac authored by David Gabriel Monk's avatar David Gabriel Monk
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Added fe-health updates

parent 7d9c1441
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2 merge requests!30Add event selection counter to link aggregator,!25Add FE Health Monitoring to MProcessor
Pipeline #4570716 failed
Stage: Static Analysis
Stage: Make Project
Stage: Pre-build Checks
Stage: Synthesis
Stage: Implementation
Stage: Package
Stage: Upload to Registry
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dependencies.yml
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− 1
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...@@ -37,7 +37,7 @@ sources: ...@@ -37,7 +37,7 @@ sources:
url: https://gitlab.cern.ch/gbtsc-fpga-support/gbt-sc.git url: https://gitlab.cern.ch/gbtsc-fpga-support/gbt-sc.git
dtc: dtc:
branch: master branch: fe_monitoring
url: https://gitlab.cern.ch/cms-tracker-phase2-data-processing/BE_firmware/dtc.git url: https://gitlab.cern.ch/cms-tracker-phase2-data-processing/BE_firmware/dtc.git
dtc-stub-processing: dtc-stub-processing:
......
top/addr_table/emp_payload.xml
+ 3
− 3
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...@@ -13,12 +13,12 @@ ...@@ -13,12 +13,12 @@
<node id="histogram1" address="0x3"/> <node id="histogram1" address="0x3"/>
</node> </node>
<node id="fe_chan" address="0x040" description="FE channel control and status" module="file://dtc_link_interface.xml" fwinfo="endpoint;width=6"/> <node id="fe_chan" address="0x200" description="FE channel control and status" module="file://dtc_link_interface.xml" fwinfo="endpoint;width=9"/>
<node id="mproc_ctrl" address="0x1ff" description="MProcessor channel control" fwinfo="endpoint;width=0"> <node id="mproc_ctrl" address="0x7ff" description="MProcessor channel control" fwinfo="endpoint;width=0">
<node id="chan_sel" mask="0x7f"/> <node id="chan_sel" mask="0x7f"/>
</node> </node>
<node id="mprocessor" address="0x200" description="MProcessor control and status" module="file://mprocessor.xml" fwinfo="endpoint;width=7"/> <node id="mprocessor" address="0x800" description="MProcessor control and status" module="file://mprocessor.xml" fwinfo="endpoint;width=7"/>
<node id="be_daq" address="0x40000000" module="file://dtc_data_aggregator.xml" fwinfo="endpoint;width=30"/> <node id="be_daq" address="0x40000000" module="file://dtc_data_aggregator.xml" fwinfo="endpoint;width=30"/>
......
top/firmware/hdl/emp_payload.vhd
+ 3
− 3
View file @ 7567b0ac
...@@ -134,8 +134,8 @@ generic map( ...@@ -134,8 +134,8 @@ generic map(
port map( port map(
clk => clk, clk => clk,
reset => rst, reset => rst,
ipbus_in => ipb_to_slaves(N_SLV_FE_CTRL), ipbus_in => ipb_to_slaves(N_SLV_FE),
ipbus_out => ipb_from_slaves(N_SLV_FE_CTRL), ipbus_out => ipb_from_slaves(N_SLV_F),
q => channel_sel, q => channel_sel,
qmask => (0 => X"0000007f") qmask => (0 => X"0000007f")
); );
...@@ -305,7 +305,7 @@ pHistogram: process(clk_p) ...@@ -305,7 +305,7 @@ pHistogram: process(clk_p)
begin begin
if rising_edge(clk_p) then if rising_edge(clk_p) then
if stubs(histogram_sel).valid = '1' and histogram_enable = '1' then if stubs(histogram_sel).valid = '1' and histogram_enable = '1' then
if stubs(histogram_sel).data(46) = '0' then if stubs(histogram_sel).data(50) = '0' then
hist0_stub <= stubs(histogram_sel); hist0_stub <= stubs(histogram_sel);
hist1_stub <= LWORD_NULL; hist1_stub <= LWORD_NULL;
else else
......
top/firmware/hdl/ipbus_decode_emp_payload.vhd
+ 17
− 17
View file @ 7567b0ac
...@@ -17,8 +17,8 @@ package ipbus_decode_emp_payload is ...@@ -17,8 +17,8 @@ package ipbus_decode_emp_payload is
subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0); subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
function ipbus_sel_emp_payload(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t; function ipbus_sel_emp_payload(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-- START automatically generated VHDL (Wed Sep 7 13:15:33 2022) -- START automatically generated VHDL (Thu Sep 15 13:10:42 2022)
constant N_SLV_FE_CTRL: integer := 0; constant N_SLV_FE: integer := 0;
constant N_SLV_CSR: integer := 1; constant N_SLV_CSR: integer := 1;
constant N_SLV_FE_CHAN: integer := 2; constant N_SLV_FE_CHAN: integer := 2;
constant N_SLV_MPROC_CTRL: integer := 3; constant N_SLV_MPROC_CTRL: integer := 3;
...@@ -38,21 +38,21 @@ package body ipbus_decode_emp_payload is ...@@ -38,21 +38,21 @@ package body ipbus_decode_emp_payload is
variable sel: ipbus_sel_t; variable sel: ipbus_sel_t;
begin begin
-- START automatically generated VHDL (Wed Sep 7 13:15:33 2022) -- START automatically generated VHDL (Thu Sep 15 13:10:42 2022)
if std_match(addr, "-0----------------00--0000000000") then if std_match(addr, "-0----------------00000000000000") then
sel := ipbus_sel_t(to_unsigned(N_SLV_FE_CTRL, IPBUS_SEL_WIDTH)); -- fe_ctrl / base 0x00000000 / mask 0x400033ff sel := ipbus_sel_t(to_unsigned(N_SLV_FE, IPBUS_SEL_WIDTH)); -- fe / base 0x00000000 / mask 0x40003fff
elsif std_match(addr, "-0----------------00--00000001--") then elsif std_match(addr, "-0----------------000000000001--") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000004 / mask 0x400033fc sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000004 / mask 0x40003ffc
elsif std_match(addr, "-0----------------00--0001------") then elsif std_match(addr, "-0----------------00001---------") then
sel := ipbus_sel_t(to_unsigned(N_SLV_FE_CHAN, IPBUS_SEL_WIDTH)); -- fe_chan / base 0x00000040 / mask 0x400033c0 sel := ipbus_sel_t(to_unsigned(N_SLV_FE_CHAN, IPBUS_SEL_WIDTH)); -- fe_chan / base 0x00000200 / mask 0x40003e00
elsif std_match(addr, "-0----------------00--0111111111") then elsif std_match(addr, "-0----------------00011111111111") then
sel := ipbus_sel_t(to_unsigned(N_SLV_MPROC_CTRL, IPBUS_SEL_WIDTH)); -- mproc_ctrl / base 0x000001ff / mask 0x400033ff sel := ipbus_sel_t(to_unsigned(N_SLV_MPROC_CTRL, IPBUS_SEL_WIDTH)); -- mproc_ctrl / base 0x000007ff / mask 0x40003fff
elsif std_match(addr, "-0----------------00--100-------") then elsif std_match(addr, "-0----------------0010000-------") then
sel := ipbus_sel_t(to_unsigned(N_SLV_MPROCESSOR, IPBUS_SEL_WIDTH)); -- mprocessor / base 0x00000200 / mask 0x40003380 sel := ipbus_sel_t(to_unsigned(N_SLV_MPROCESSOR, IPBUS_SEL_WIDTH)); -- mprocessor / base 0x00000800 / mask 0x40003f80
elsif std_match(addr, "-0----------------01--0---------") then elsif std_match(addr, "-0----------------01000---------") then
sel := ipbus_sel_t(to_unsigned(N_SLV_MEM1, IPBUS_SEL_WIDTH)); -- mem1 / base 0x00001000 / mask 0x40003200 sel := ipbus_sel_t(to_unsigned(N_SLV_MEM1, IPBUS_SEL_WIDTH)); -- mem1 / base 0x00001000 / mask 0x40003e00
elsif std_match(addr, "-0----------------10--0---------") then elsif std_match(addr, "-0----------------10000---------") then
sel := ipbus_sel_t(to_unsigned(N_SLV_MEM2, IPBUS_SEL_WIDTH)); -- mem2 / base 0x00002000 / mask 0x40003200 sel := ipbus_sel_t(to_unsigned(N_SLV_MEM2, IPBUS_SEL_WIDTH)); -- mem2 / base 0x00002000 / mask 0x40003e00
elsif std_match(addr, "-1------------------------------") then elsif std_match(addr, "-1------------------------------") then
sel := ipbus_sel_t(to_unsigned(N_SLV_BE_DAQ, IPBUS_SEL_WIDTH)); -- be_daq / base 0x40000000 / mask 0x40000000 sel := ipbus_sel_t(to_unsigned(N_SLV_BE_DAQ, IPBUS_SEL_WIDTH)); -- be_daq / base 0x40000000 / mask 0x40000000
-- END automatically generated VHDL -- END automatically generated VHDL
......
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